Motorola PowerQUICC II MPC8280 Series Reference Manual page 580

Communications Processor (CP)
Data
Scheduler
Sequencer
Microcode
ROM
Figure 14-2. Communications Processor (CP) Block Diagram
14-6
Freescale Semiconductor, Inc.
Communications Processor (CP)
Timer
Special
Registers
Source Buses
Destination Bus
Block Transfer
Data
Instruction
Decoder
To all units
Dual-Port RAM
Bus
Interface
MPC8280 PowerQUICC II Family Reference Manual
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Execution
Unit
Load/Store
Module
Unit
(BTM)
60x Bus
Local Bus
General-
Purpose
Registers
Address
Data
DMA
Address
Data
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