Motorola PowerQUICC II MPC8280 Series Reference Manual page 1029

than MDA (maximum delay allowed), the APC begins scheduling channels according to
the MCR parameter. If the delay, however, drops below MDA, the APC again schedules
channels according to the PCR. Note that in order to guarantee a minimum cell rate for
UBR+ channels, there must be enough bandwidth to simultaneously send all possible
channels at the MCR. See Section 31.10.2.3.7, "UBR+ Protocol-Specific TCTE."
31.3.6 Determining the Priority of an ATM Channel
The priority mechanism is implemented by adding priority table levels, which point to
separate scheduling tables; see Section 31.10.4, "APC Data Structure." The APC flow
control services the APC_LEVEL1 slots first. If there are no cells to send, the APC goes to
the next priority level. The APC has up to eight priority levels with APC_LEVEL8 being
the lowest. The user specifies the priority of an ATM channel when issuing the
command; see Section 31.14, "ATM Transmit Command."
TRANSMIT
The real-time channels, CBR and VBR-RT, should be inserted in APC_LEVEL1;
non-real-time channels, VBR-NRT, ABR, and UBR should be inserted in lower priority
levels.
31.4 VCI/VPI Address Lookup Mechanism
The MPC8280 supports two ways to look up addresses for incoming cells:
• External CAM lookup
• Address compression
Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects
the mechanism. Both mechanisms are described in the following sections.
31.4.1 External CAM Lookup
An external CAM is usually used when the range of VCI/VPI values varies widely or is
unknown. Clearing GMODE[ALM] selects the external CAM address lookup mechanism.
If there is no match in the external CAM, the cell is considered a misinserted cell. The
external CAM can point to internal or external channels (channels whose connection table
resides in external memory). The CAM input, shown in Figure 31-3, is the 32-bit cell
address: PHY address, GFC + VPI, and VCI.
The bus atomicity mechanism for CAM accesses may not
function correctly when the CPM performs a DMA access to an
external CAM device. This only impacts systems in which
multiple CPMs will access the CAM.
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
NOTE
For More Information On This Product,
Go to: www.freescale.com
VCI/VPI Address Lookup Mechanism
ATM
31-15