Motorola MPC8240 User Manual

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MPC8240 Integrated Processor

User's Manual

MPC8240UM/D

Rev 1, 1/2001

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Summary of Contents for Motorola MPC8240

Page 1 MPC8240 Integrated Processor User’s Manual MPC8240UM/D Rev 1, 1/2001 ™...
Page 2 Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or...
Page 3 Overview Signal Descriptions and Clocking Address Maps Configuration Registers PowerPC Processor Core MPC8240 Memory Interface PCI Bus Interface DMA Controller Message Unit (I C Interface Embedded Programmable Interrupt Controller (EPIC) Central Control Unit Error Handling Power Management Debug Features Programmable I/O and Watchpoint...
Page 4 Overview Signal Descriptions and Clocking Address Maps Configuration Registers PowerPC Processor Core MPC8240 Memory Interface PCI Bus Interface DMA Controller Message Unit (I C Interface Embedded Programmable Interrupt Controller (EPIC) Central Control Unit Error Handling Power Management Debug Features Programmable I/O and Watchpoint...
Page 5: Table Of Contents
Page Title Number Number About This Book Chapter 1 Overview MPC8240 Integrated Processor Overview............1-1 1.1.1 MPC8240 Integrated Processor Features............1-3 1.1.2 MPC8240 Integrated Processor Applications..........1-5 Processor Core Overview ................... 1-7 Peripheral Logic Bus..................1-10 Peripheral Logic Overview ................1-11 1.4.1...
Page 6 Lock (LOCK)—Input ................2-13 2.2.1.10 Target Ready (TRDY) ................2-13 2.2.1.10.1 Target Ready (TRDY)—Output ............2-13 2.2.1.10.2 Target Ready (TRDY)—Input.............. 2-14 2.2.1.11 Parity Error (PERR).................. 2-14 2.2.1.11.1 Parity Error (PERR)—Output .............. 2-14 2.2.1.11.2 Parity Error (PERR)—Input ..............2-14 MPC8240 Integrated Processor User’s Manual...
Page 7 CONTENTS Paragraph Page Title Number Number 2.2.1.12 System Error (SERR) ................2-14 2.2.1.12.1 System Error (SERR)—Output ............2-15 2.2.1.12.2 System Error (SERR)—Input ............... 2-15 2.2.1.13 Stop (STOP)....................2-15 2.2.1.13.1 Stop (STOP)—Output ................2-15 2.2.1.13.2 Stop (STOP)—Input ................2-15 2.2.1.14 Interrupt Request (INTA)—Output............2-15 2.2.1.15 ID Select (IDSEL)—Input ................
Page 8 Debug Clock (CKO)—Output ..............2-34 Clocking ......................2-34 2.3.1 Clocking Method ..................2-34 2.3.2 DLL Operation and Locking................. 2-35 2.3.3 Clock Synchronization.................. 2-36 2.3.4 Clocking System Solution Examples............2-37 Configuration Signals Sampled at Reset............2-38 viii MPC8240 Integrated Processor User’s Manual...
Page 9 CONTENTS Paragraph Page Title Number Number Chapter 3 Address Maps Address Map B ....................3-1 Address Map B Options..................3-7 3.2.1 Processor Compatibility Hole and Alias Space ..........3-7 3.2.2 PCI Compatibility Hole and Alias Space ............3-9 Address Translation ..................3-11 3.3.1 Inbound PCI Address Translation..............
Page 10 Hardware Implementation-Dependent Register 0 (HID0) ....5-13 5.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ....5-16 5.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ....5-17 5.3.1.2.4 Processor Version Register (PVR) ............5-17 5.3.2 PowerPC Instruction Set and Addressing Modes ......... 5-18 MPC8240 Integrated Processor User’s Manual...
Page 11 SDRAM Address Multiplexing ..............6-10 6.2.3 SDRAM Memory Data Interface..............6-13 6.2.4 SDRAM Power-On Initialization ..............6-16 6.2.5 MPC8240 Interface Functionality for JEDEC SDRAMs ......6-17 6.2.6 SDRAM Burst and Single-Beat Transactions ..........6-18 6.2.7 SDRAM Page Mode ..................6-19 6.2.7.1 SDRAM Paging in Sleep Mode..............
Page 12 ROM/Flash Interface Write Timing ............. 6-84 6.4.6 PCI-to-ROM/Port X Transaction Example........... 6-84 6.4.7 Port X Interface..................... 6-89 Chapter 7 PCI Bus Interface PCI Interface Overview ..................7-1 7.1.1 The MPC8240 as a PCI Initiator..............7-2 MPC8240 Integrated Processor User’s Manual...
Page 13 CONTENTS Paragraph Page Title Number Number 7.1.2 The MPC8240 as a PCI Target ............... 7-3 7.1.3 PCI Signal Output Hold Timing ..............7-3 PCI Bus Arbitration .................... 7-4 7.2.1 Internal Arbitration for PCI Bus Access............7-4 7.2.1.1 Processor-Initiated Transactions to PCI Bus ..........7-5 7.2.1.2...
Page 14 Error Reporting ..................... 7-32 PCI Host and Agent Modes ................7-32 7.7.1 PCI Initialization Options ................7-32 7.7.2 Accessing the MPC8240 Configuration Space..........7-33 7.7.3 PCI Configuration Cycle Retry Capability in Agent Mode......7-34 7.7.4 PCI Address Translation Support ..............7-34 7.7.4.1...
Page 15 CONTENTS Paragraph Page Title Number Number 8.6.1 Descriptors in Big-Endian Mode ..............8-14 8.6.2 Descriptors in Little-Endian Mode ............... 8-14 DMA Register Descriptions................8-15 8.7.1 DMA Mode Registers (DMRs)..............8-15 8.7.2 DMA Status Registers (DSRs) ..............8-18 8.7.3 Current Descriptor Address Registers (CDARs) .......... 8-19 8.7.4 Source Address Registers (SARs) ..............
Page 16 Generation of SCK when SDA Low............10-15 10.4.7 Slave Mode Interrupt Service Routine............10-16 10.4.7.1 Slave Transmitter and Received Acknowledge ........10-16 10.4.7.2 Loss of Arbitration and Forcing of Slave Mode ........10-16 10.4.8 Interrupt Service Routine Flowchart............10-16 MPC8240 Integrated Processor User’s Manual...
Page 17 CONTENTS Paragraph Page Title Number Number Chapter 11 Embedded Programmable Interrupt Controller (EPIC) Unit 11.1 EPIC Unit Overview ..................11-1 11.1.1 EPIC Features Summary................11-2 11.1.2 EPIC Interface Signal Description..............11-2 11.1.3 EPIC Block Diagram ..................11-3 11.2 EPIC Register Summary ................... 11-4 11.3 EPIC Unit Interrupt Protocol ................
Page 18 System Reset....................13-3 13.2.2 Processor Core Error Signal (mcp) .............. 13-3 13.2.3 PCI Bus Error Signals................... 13-4 13.2.3.1 System Error (SERR) ................13-4 13.2.3.2 Parity Error (PERR).................. 13-5 13.2.3.3 Nonmaskable Interrupt (NMI) ..............13-5 xviii MPC8240 Integrated Processor User’s Manual...
Page 19 Processor Sleep Mode................14-6 14.2.4 Power Management Software Considerations..........14-6 14.3 Peripheral Logic Power Management............... 14-7 14.3.1 MPC8240 Peripheral Power Mode Transitions ..........14-7 14.3.2 Peripheral Power Management Modes ............14-9 14.3.2.1 Peripheral Logic Full Power Mode............14-9 14.3.2.2 Peripheral Logic Doze Mode..............14-9 14.3.2.3...
Page 20 15.6 JTAG/Testing Support ..................15-21 15.6.1 JTAG Signals....................15-21 15.6.2 JTAG Registers and Scan Chains ............... 15-22 15.6.2.1 Bypass Register ..................15-22 15.6.2.2 Boundary-Scan Registers................ 15-22 15.6.2.3 Instruction Register................. 15-22 15.6.2.4 TAP Controller ..................15-22 MPC8240 Integrated Processor User’s Manual...
Page 21 CONTENTS Paragraph Page Title Number Number Chapter 16 Programmable I/O and Watchpoint 16.1 Watchpoint Interface Signal Description............16-2 16.2 Watchpoint Registers ..................16-3 16.2.1 Watchpoint Register Address Map ............... 16-3 16.2.2 Watchpoint Trigger Registers............... 16-4 16.2.3 Watchpoint Mask Registers ................16-6 16.2.4 Watchpoint Control Register (WP_CONTROL)..........
Page 22 Required Physical Address Register (RPA) ..........E-22 E.2.5 Instruction Address Breakpoint Register (IABR)......... E-23 MPC8240-Specific Registers................E-23 E.3.1 Hardware Implementation-Dependent Register 0 (HID0)......E-24 E.3.2 Hardware Implementation-Dependent Register 1 (HID1)......E-27 E.3.3 Hardware Implementation-Dependent Register 2 (HID2)......E-28 xxii MPC8240 Integrated Processor User’s Manual...
Page 23 System Using an Integrated MPC8240 as a Host Processor......... 1-5 Embedded System Using an MPC8240 as a Peripheral Processor....... 1-6 Embedded System Using an MPC8240 as a Distributed Processor ......1-7 MPC8240 Integrated Processor Core Block Diagram ..........1-9 MPC8240 Peripheral Logic Block Diagram............... 1-11 MPC8240 Signal Groupings ..................
Page 24 Memory Control Configuration Register 3 (MCCR3)—0xF8 ........4-48 4-32 Memory Control Configuration Register 4 (MCCR4)—0xFC........4-51 MPC8240 Integrated Processor Core Block Diagram ..........5-2 MPC8240 Programming Model—Registers............... 5-12 Hardware Implementation Register 0 (HID0) ............5-13 Hardware Implementation Register 1 (HID1) ............5-16 Hardware Implementation-Dependent Register 2 (HID2)..........
Page 25 ILLUSTRATIONS Figure Page Title Number Number 6-17 SDRAM Refresh Period ..................... 6-31 6-18 SDRAM Bank Staggered CBR Refresh Timing............6-33 6-19 SDRAM Self Refresh Entry..................6-35 6-20 SDRAM Self Refresh Exit..................6-35 6-21 Processor Burst Reads from SDRAM................. 6-37 6-22 Processor Single-Beat Reads from SDRAM ..............
Page 26 Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 4 of 4) ....6-89 6-64 Port X Peripheral Interface Block Diagram..............6-90 6-65 Example of Port X Peripheral Connected to the MPC8240 ........6-91 6-66 Example of Port X Peripheral Connected to the MPC8240 ........6-92 6-67 Port X Example Read Access Timing ................
Page 27 Processor Current Task Priority Register (PCTPR)..........11-27 11-18 Processor Interrupt Acknowledge Register (IACK) ..........11-28 11-19 Processor End of Interrupt Register (EOI)..............11-28 12-1 MPC8240 Internal Buffer Organization ..............12-2 12-2 Processor/Local Memory Buffers ................12-3 12-3 Processor/PCI Buffers....................12-4 12-4 PCI/Local Memory Buffers ..................
Page 28 Figure Page Title Number Number 14-1 MPC8240 Peripheral Logic Power States..............14-7 15-1 Example PCI Address Attribute Signal Timing for Burst Read Operations ....15-4 15-2 Example PCI Address Attribute Signal Timing for Burst Write Operations....15-5 15-3 64-Bit Mode, DRAM and SDRAM Physical Address for Debug ......15-6 15-4 32-Bit Mode, DRAM and SDRAM Physical Address for Debug ......
Page 29 One-Byte Transfer to PCI I/O Space—Little-Endian Mode........B-12 B-10 Two-Byte Transfer to PCI I/O Space—Little-Endian Mode........B-13 B-11 Four-Byte Transfer to PCI I/O Space—Little-Endian Mode........B-14 MPC8240 Processor Programming Model—Registers ..........E-3 General-Purpose Registers (GPRs)................E-4 Floating-Point Registers (FPRs) ...................E-4 Condition Register (CR) ....................E-4 Floating-Point Status and Control Register (FPSCR)...........E-6 XER Register ........................E-8...
Page 30 HASH1 and HASH2 Registers ...................E-22 E-25 Required Physical Address Register (RPA) ...............E-22 E-26 Instruction Address Breakpoint Register (IABR)............E-23 E-27 Hardware Implementation Register 0 (HID0) ............E-24 E-28 Hardware Implementation Register 1 (HID1) ............E-27 E-29 Hardware Implementation-Dependent Register 2 (HID2)..........E-28 MPC8240 Integrated Processor User’s Manual...
Page 31 Embedded Utilities Peripheral Control and Status Register Summary ...... 3-20 Internal Register Access Port Locations ............... 4-1 MPC8240 Configuration Registers Accessible from the Processor Core ....4-5 MPC8240 Configuration Registers Accessible from the PCI Bus ....... 4-9 PCI Configuration Space Header Summary ............... 4-10 Bit Settings for PCI Command Register—0x04............
Page 32 Exceptions and Conditions ..................5-28 Integer Divide Latency ....................5-33 5-10 Major Differences between MPC8240’s Core and the MPC603e User’s Manual ..5-34 Memory Interface Signal Summary................6-3 Memory Address Signal Mappings ................6-5 SDRAM Data Bus Lane Assignments................6-7 Unsupported Multiplexed Row and Column Address Bits...........
Page 33 Memory Interface Configuration Register Fields ............6-55 6-22 FPM or EDO Timing Parameters ................6-57 6-23 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 0:31)....6-63 6-24 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 32:63)....6-63 6-25 FPM or EDO DRAM Power Saving Modes Refresh Configuration......
Page 34 EUMBBAR Offsets for GTBCRs................11-21 11-15 GTBCR Field Descriptions..................11-22 11-16 EUMBBAR Offsets for GTVPRs................11-22 11-17 GTVPR Field Descriptions ..................11-23 11-18 EUMBBAR Offsets for GTDRs ................11-23 11-19 GTDR Field Descriptions ..................11-24 xxxiv MPC8240 Integrated Processor User’s Manual...
Page 35 Address Map A—PCI I/O Master View..............A-2 Byte Lane Translation in Big-Endian Mode..............B-2 Processor Address Modification for Individual Aligned Scalars .........B-6 MPC8240 Address Modification for Individual Aligned Scalars.........B-6 Byte Lane Translation in Little-Endian Mode ..............B-6 Complete Instruction List Sorted by Mnemonic............D-1 Complete Instruction List Sorted by Opcode...............
Page 36 TABLES Table Page Title Number Number Integer Arithmetic Instructions .................. D-17 Integer Compare Instructions..................D-18 Integer Logical Instructions ..................D-18 Integer Rotate Instructions..................D-18 Integer Shift Instructions.................... D-19 Floating-Point Arithmetic Instructions7 ..............D-19 Floating-Point Multiply-Add Instructions7 ............... D-20 D-10 Floating-Point Rounding and Conversion Instructions7..........D-20 D-11 Floating-Point Compare Instructions7...............
Page 37 TABLES Table Page Title Number Number D-46 PowerPC Instruction Set Legend ................D-38 Bit Settings for CR0 Field of CR..................E-4 Bit Settings for CR1 Field of CR..................E-5 CRn Field Bit Settings for Compare Instructions ............E-5 FPSCR Bit Settings.......................E-6 Floating-Point Result Flags in FPSCR .................E-8 XER Bit Definitions......................E-8 BO Operand Encodings ....................E-9 MSR Bit Settings ......................E-13...
Page 38 TABLES Table Page Title Number Number xviii MPC8240 Integrated Processor User’s Manual...
Page 39: About This Book
About This Book The primary objective of this user’s manual is to deﬁne the functionality of the MPC8240 PowerPC™ integrated processor. The MPC8240 has a processor core based on the PowerPC 603e™ low-power microprocessor; it also performs many peripheral functions on-chip.
Page 40: Overview
MPC8240’s external signals. It describes each signal’s behavior when the signal is asserted and negated and when the signal is an input or an output. • Chapter 3, “Address Maps,” describes how the MPC8240 in host mode supports the address map B conﬁguration. •...
Page 41: Address Maps
TRIG_IN signal, and how the TRIG_OUT signal can be generated based on programmable watchpoints on the internal processor bus. • Appendix A, “Address Map A.” The MPC8240 supports two address maps. This appendix describes address map A. • Appendix B, “Bit and Byte Ordering,” describes the big- and little-endian modes and provides examples of each.
Page 42 (Chapter 1) of an implementation’s user’s manual. • PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors: MPCBUSIF/AD (Motorola order #) provides a detailed functional description of the 60x bus interface, as implemented on the 601, 603, and 604 family of PowerPC xlii MPC8240 Integrated Processor User’s Manual...
Page 43 60x family of PowerPC microprocessors. • PowerPC Microprocessor Family: The Programmer’s Reference Guide: MPCPRG/D (Motorola order #) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.
Page 44: Acronyms And Abbreviations
Data TLB compare Decrementer register DIMM Dual in-line memory module DRAM Dynamic random access memory DMISS Data TLB miss address DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer xliv MPC8240 Integrated Processor User’s Manual...
Page 45 Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Effective address External access register Error checking and correction Extended data out DRAM ErrDR Error detection register ErrEnR Error enabling register FIFO First-in-ﬁrst-out Floating-point register FPSCR Floating-point status and control register Floating-point unit General-purpose register HASH1...
Page 46 SIMM Single in-line memory module Special-purpose register Segment register SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 System register unit Test access port Time base facility Time base lower register xlvi MPC8240 Integrated Processor User’s Manual...
Page 47 Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Time base upper register Translation lookaside buffer Transistor-to-transistor logic UIMM Unsigned immediate value UISA User instruction set architecture Unit under test Voltage-controlled oscillator Virtual environment architecture Write-after-read Write-after-write WIMG Write-through/caching-inhibited/memory-coherency enforced/guarded bits Register used for indicating conditions such as carries and overﬂows for integer operations...
Page 48 Acronyms and Abbreviations xlviii MPC8240 Integrated Processor User’s Manual...
Page 49: Overview
For errata or revisions to this document, refer to the web site at http://www.motorola.com/semiconductors. 1.1 MPC8240 Integrated Processor Overview The MPC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC processor core, as shown in Figure 1-1. Chapter 1. Overview...
Page 50: Mpc8240 Integrated Processor Functional Block Diagram
OSC In PCI Interface Request/Grant Pairs Figure 1-1. MPC8240 Integrated Processor Functional Block Diagram The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, a message unit (and I O controller), and an I C controller. The processor core is a full-featured, high-performance processor with ﬂoating-point support,...
Page 51: Mpc8240 Integrated Processor Features
The processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. The MPC8240 can be used as either a PCI host or PCI agent controller. 1.1.1 MPC8240 Integrated Processor Features This section summarizes the features of the MPC8240.
Page 52: Dma Controller
• Dynamic power management—Supports 60x nap, doze, and sleep modes • Programmable input and output signals with watchpoint capability • Built-in PCI bus performance monitor facility — Debug features – Memory attribute and PCI attribute signals – Debug address signals MPC8240 Integrated Processor User’s Manual...
Page 53: Mpc8240 Integrated Processor Applications
— Lockable L1 cache—entire cache or on a per-way basis 1.1.2 MPC8240 Integrated Processor Applications The MPC8240 can be used for control processing in applications such as routers, switches, multi-channel modems, network storage, image display systems, enterprise I/O processor, Internet access device (IAD), disk controller for RAID systems, and copier/printer board control.
Page 54: Embedded System Using An Mpc8240 As A Peripheral Processor
Figure 1-4 shows the MPC8240 as a distributed I/O processing device. The PCI-to-PCI bridge shown could be of the PCI type 0 variety. The MPC8240 would not be part of the system conﬁguration map. This conﬁguration is useful in applications such as RAID controllers, where the I/O devices shown are SCSI controllers, or multi-port network controllers where the devices shown are Ethernet controllers.
Page 55: Processor Core Overview
Figure 1-4. Embedded System Using an MPC8240 as a Distributed Processor 1.2 Processor Core Overview The MPC8240 contains an embedded version of the PowerPC 603e™ processor. For detailed information regarding the processor refer to the following: • MPC603e & EC603e User’s Manual (Those chapters that describe the...
Page 56 TLB and BAT array, the BAT translation takes priority. As an added feature to the processor core, the MPC8240 can lock the contents of one to three ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache.
Page 57: Mpc8240 Integrated Processor Core Block Diagram
Control Decrementer 16Kbyte 16Kbyte Tags Tags JTAG/COP Clock D Cache I Cache Interface Multiplier Touch Load Buffer PERIPHERAL LOGIC BUS INTERFACE Copyback Buffer 32-Bit Address Bus 32-/64-Bit Data Bus Figure 1-5. MPC8240 Integrated Processor Core Block Diagram Chapter 1. Overview...
Page 58: Peripheral Logic Bus
Peripheral Logic Bus 1.3 Peripheral Logic Bus The MPC8240 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies allowing the designer to balance performance and power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL.
Page 59: Peripheral Logic Overview
32-Bit Five PCI Interface Request/Grant Pairs Figure 1-6. MPC8240 Peripheral Logic Block Diagram 1.4.1 Peripheral Logic Features Major features of the peripheral logic are as follows: • Peripheral logic bus — Supports various operating frequencies and bus divider ratios — 32-bit address bus, 64-bit data bus —...
Page 60: Peripheral Logic Functional Units
1.4.2 Peripheral Logic Functional Units The peripheral logic consists of the following major functional units: • Peripheral logic bus interface • Memory interface • PCI interface — PCI bus arbitration unit — Address maps and translation 1-12 MPC8240 Integrated Processor User’s Manual...
Page 61: Memory System Interface
MPC8240. Some devices may require a small amount of external logic to generate properly address strobes, chip selects, and other signals. The MPC8240 is designed to control a 32- or 64-bit data path to main memory DRAM or SDRAM. For a 32-bit data path, the MPC8240 can be conﬁgured to check and generate byte parity using four parity bits.
Page 62: Peripheral Component Interconnect (Pci) Interface
MPC8240 in agent mode. Note that address translation is supported only for agent mode; it is not supported when the MPC8240 is operating in host mode. Also note that since agent mode is supported only for address map B, address translation is supported only for address map B.
Page 63: Byte Ordering
Peripheral Logic Overview 1.4.4.3 Byte Ordering The MPC8240 allows the processor to run in either big- or little-endian mode (except for the initial boot code which must run in big-endian mode). 1.4.4.4 PCI Agent Capability In certain applications, the embedded system architecture dictates that the MPC8240 act as a peripheral processor.
Page 64: Inbound And Outbound Message Registers
Peripheral Logic Overview 1.4.6.2 Inbound and Outbound Message Registers The MPC8240 contains two 32-bit inbound message registers and two 32-bit outbound message registers. The inbound registers allow a remote host or PCI master to write a 32-bit value, causing an interrupt to the processor core. The outbound registers allow the processor core to write an outbound message which causes the outbound interrupt signal INTA to assert.
Page 65: Integrated Pci Bus And Sdram Clock Generation
1.4.9 Integrated PCI Bus and SDRAM Clock Generation There are two PCI bus clocking solutions directed towards different system requirements. For systems where the MPC8240 is the host controller with a minimum number of clock loads, ﬁve clock fanout buffers are provided on-chip.
Page 66: Power Management
The MPC8240 has independent power management functionality for both the processor core and the peripheral logic.The MPC8240 provides hardware support for three levels of programmable power reduction for both the processor and the peripheral logic. Doze, nap, and sleep modes are invoked by register programming—HID0 in the case of the processor...
Page 67: Programmable I/O Signals With Watchpoint
1.6 Programmable I/O Signals with Watchpoint The MPC8240 programmable I/O facility allows the system designer to monitor the peripheral logic bus. Up to two watchpoints and their respective 4-bit countdown values can be programmed. When the programmed threshold of the selected watchpoint is reached, an external trigger signal is generated.
Page 68: Memory Attribute And Pci Attribute Signals
1.7.4 Error Injection/Capture on Data Path The MPC8240 provides hardware to exercise and debug the ECC and parity logic by allowing the user to inject multi-bit stuck-at faults onto the peripheral logic or memory data/parity buses and to capture the data/parity output on receipt of an ECC or parity error.
Page 69: Signal Overview
Chapter 2 Signal Descriptions and Clocking This chapter provides descriptions of the MPC8240’s external signals. It describes each signal’s behavior when the signal is asserted and negated and when the signal is an input or an output. NOTE: A bar over a signal name indicates that the signal is active low—for example, AS (address strobe).
Page 70 • Test/conﬁguration signals • Clock signals Figure 2-1 illustrates the external signals of the MPC8240, showing how the signals are grouped. Refer to the MPC8240 Hardware Speciﬁcation for a pinout diagram showing actual pin numbers and a listing of all the electrical and mechanical speciﬁcations.
Page 71: Mpc8240 Signal Groupings
Debug DA[15:11], DA2 SDRAS SDCAS PLL_CFG[0:4]/DA[10:6]* RCS0 RCS1 Test/ Configuration IRQ0/S_INT TRST IRQ1/S_CLK EPIC Control IRQ2/S_RST C Control IRQ3/S_FRAME IRQ4/L_INT * Reference Table 15-5 Memory Debug Address Signal Deﬁnitions Figure 2-1. MPC8240 Signal Groupings Chapter 2. Signal Descriptions and Clocking...
Page 72: Signal Cross Reference
The following sections are intended to provide a quick summary of signal functions. Table 2-1 provides an alphabetical cross-reference to the signals of the MPC8240. It details the signal name, interface, alternate functions, number of signals, whether the signal is an input, output, or bidirectional, and ﬁnally a pointer to the section in this chapter where the...
Page 73 Signal Overview Table 2-1. MPC8240 Signal Cross Reference (Continued) Alternate Signal Signal Name Interface Pins Section # Function (s) IRQ2 Interrupt 2 EPIC Control S_RST 2.2.3.1 IRQ3 Interrupt 3 EPIC Control S_FRAME 2.2.3.1 IRQ4 Interrupt 4 EPIC Control L_INT 2.2.3.1...
Page 74: Output Signal States During Reset
— 2.2.2.5 The MPC8240 samples these signals at the negation of reset to determine the reset conﬁguration. After they are sampled, they assume their normal functions. See Section 2.4, “Conﬁguration Signals Sampled at Reset,” for more information about their function during reset.
Page 75: Detailed Signal Descriptions
2.2.1 PCI Interface Signals This section provides descriptions of the PCI interface signals on the MPC8240. Note that throughout this manual, signals and bits of the PCI interface are referenced in little-endian format. For more information on the operation of the MPC8240 PCI interface, see Chapter 7, “PCI Bus Interface.”...
Page 76: Pci Bus Request (Req[4:0])—Input
PCI bus grant input for the MPC8240, and it is asserted when the external arbiter is granting the use of the PCI bus to the MPC8240. Note that if the REQ0 input signal is asserted prior to the need to run a PCI transaction, then the MPC8240 GNT0 signal will not assert (the bus is parked) when a PCI transaction is to be run.
Page 77: Pci Bus Grant (Gnt[4:0])—Internal Arbiter Disabled
2.2.1.2.2 PCI Bus Grant (GNT[4:0])—Internal Arbiter Disabled The MPC8240 PCI arbiter is disabled by a high value on the reset conﬁguration pin MAA2 or by the clearing of bit 15 of the PCI arbitration control register. In this case, the GNT0 becomes the PCI bus request output for the MPC8240 and is asserted when the MPC8240 needs to run a PCI transaction.
Page 78: Parity (Par)
Detailed Signal Descriptions 2.2.1.4 Parity (PAR) The PCI parity (PAR) signal is both an input and output signal on the MPC8240. See Section 7.6.1, “PCI Parity,” for more information on PCI parity. 2.2.1.4.1 Parity (PAR)—Output Following is the state meaning for PAR as an output signal.
Page 79: Command/Byte Enable (C/Be[3:0])—Input
During the data phase, C/BE[3:0] indicate which byte lanes are valid. 2.2.1.6 Device Select (DEVSEL) The device select (DEVSEL) signal is both an input and output on the MPC8240. 2.2.1.6.1 Device Select (DEVSEL)—Output Following is the state meaning for DEVSEL as an output.
Page 80: Device Select (Devsel)—Input
Negated—Indicates that the transaction is in the ﬁnal data phase or that the bus is idle. 2.2.1.8 Initiator Ready (IRDY) The initiator ready (IRDY) signal is both an input and output on the MPC8240. 2.2.1.8.1 Initiator Ready (IRDY)—Output Following is the state meaning for IRDY as an output.
Page 81: Initiator Ready (Irdy)—Input
PCI transaction. If FRAME is negated, it indicates the PCI bus is idle. 2.2.1.9 Lock (LOCK)—Input The lock (LOCK) signal is an input on the MPC8240. See Section 7.5, “Exclusive Access,” for more information. Following is the state meaning for the LOCK input signal. State Meaning Asserted—Indicates that a master is requesting exclusive access to...
Page 82: Target Ready (Trdy)—Input
(on a write). 2.2.1.11 Parity Error (PERR) The PCI parity error (PERR) signal is both an input and output signal on the MPC8240. See Section 13.2.3.2, “Parity Error (PERR),” and Section 4.8.2, “Error Enabling and Detection Registers,”...
Page 83: System Error (Serr)—Output
Negated—Indicates no error. 2.2.1.13 Stop (STOP) The stop (STOP) signal is both an input and output signal on the MPC8240. Refer to Section 7.4.3.2, “Target-Initiated Termination,” for more information on the use of the STOP signal.
Page 84: Id Select (Idsel)—Input
The MPC8240 must use the method described in Section 4.1, “Conﬁguration Register Access,” to access its own conﬁguration registers. If the MPC8240 is in host mode and other PCI agents do not need to access the MPC8240’s conﬁguration space, then it is recommended that this signal be pulled down.
Page 85: Column Address Strobe (Cas[0:7])—Output
Detailed Signal Descriptions 2.2.2.2 Column Address Strobe (CAS[0:7])—Output The eight column address strobe (CAS[0:7]) signals are outputs on the MPC8240. CAS0 connects to the most-signiﬁcant byte select. CAS7 connects to the least-signiﬁcant byte select. When the MPC8240 is operating in 32-bit mode (see MCCR1[DBUS_SIZ[0:1]), the CAS[0:3] signals are used.
Page 86: Write Enable (We)—Output
Detailed Signal Descriptions 2.2.2.5 Write Enable (WE)—Output The write enable (WE) signal is an output on the MPC8240. For SDRAM, WE is part of the SDRAM command encoding. See Section 6.2, “SDRAM Interface Operation,” for more information. Following are the state meaning and timing comments for the WE output signal for DRAM, ECO and Flash writes.
Page 87: Memory Data Bus (Mdh[0:31], Mdl[0:31])
MDL0 low during reset. When the MPC8240 is conﬁgured with a 32-bit data bus, the bus operates in the same way as when conﬁgured with a 64-bit data bus, with the exception that only MDH[0:31] is used, and MDL[0:31] can be left ﬂoating.
Page 88: Memory Data Bus (Mdh[0:31], Mdl[0:31])—Output
Timing Comments Assertion/Negation—For a memory read transaction, the data bus signals are valid at a time dependent on the memory interface conﬁguration parameters. Refer to Chapter 4, “Conﬁguration Registers,” and Chapter 6, “MPC8240 Memory Interface,” for more information. 2.2.2.10 Data Parity/ECC (PAR[0:7]) The eight data parity/ECC (PAR[0:7]) signals are both input and output signals on the MPC8240.
Page 89: Data Parity (Par[0:7])—Input
RCS0 or RCS1. 2.2.2.12 SDRAM Clock Enable (CKE)—Output The SDRAM clock enable (CKE) signal is an output on the MPC8240 (and is also used as a reset conﬁguration input signal). CKE is part of the SDRAM command encoding. See Section 6.2, “SDRAM Interface Operation,” for more information. Following are the state meaning and timing comments for the CKE output signal.
Page 90: Sdram Column Address Strobe (Sdcas)—Output
Negation—Controlled by the ROMFAL and ROMNAL parameters of the MCCR1 register. 2.2.2.16 ROM Bank 1 Select (RCS1)—Output The ROM bank 1 select (RCS1) signal is an output on the MPC8240. Following are the state meaning and timing comments for the RCS1 output signal. State Meaning Asserted—Selects ROM bank 1 for a read access or Flash bank 1 for...
Page 91: Flash Output Enable (Foe)—Output
Detailed Signal Descriptions 2.2.2.17 Flash Output Enable (FOE)—Output The Flash output enable (FOE) signal is an output on the MPC8240 (and a reset conﬁguration input signal). Following are the state meaning and timing comments for the FOE output signal. State Meaning Asserted—Enables Flash output for the current read access.
Page 92: Serial Interrupt Mode Signals
State Meaning Asserted/Negated—Represents the interrupts for up to 16 external interrupt sources with individually programmable sense and polarity. These interrupts are clocked in to the MPC8240 by the S_CLK signal. 2.2.3.2.2 Serial Interrupt Clock (S_CLK)—Output This output serves as the serial clock that the external interrupt source must use for driving the 16 interrupts onto the S_INT signal.
Page 93: Serial Clock (Scl)
I C signals. 2.2.4.1 Serial Data (SDA) This signal is an input when the MPC8240 is in a receiving mode and an output when it is transmitting (as an I C master or a slave). 2.2.4.1.1 Serial Data (SDA)—Output...
Page 94: Hard Reset
Detailed Signal Descriptions 2.2.5.1 Hard Reset The two hard reset signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to guarantee normal operation. Together, HRST_CPU and HRST_CTRL cause the MPC8240 to abort all current internal and external transactions, and set all registers to their default values.
Page 95: Machine Check (Mcp)-Output
SRESET is negated, the processor vectors to the system reset vector. 2.2.5.3 Machine Check (MCP)—Output The MCP signal is driven by the MPC8240 when a machine check error is generated by any of the conditions described in Chapter 13, “Error Handling,” for generating the internal mcp signal.
Page 96: System Management Interrupt (Smi)-Input
Timing Comments Assertion/Negation—May occur on any cycle. 2.2.5.8 Quiesce Acknowledge (QACK)—Output The quiesce acknowledge (QACK) signal is an output on the MPC8240.It is also a reset conﬁguration input signal. See Chapter 14, “Power Management,” for more information 2-28 MPC8240 Integrated Processor User’s Manual...
Page 97: Watchpoint Trigger Signals
Watchpoint Trigger In (TRIG_IN)—Input 2.2.5.9.1 The watchpoint trigger in (TRIG_IN) signal is an input on the MPC8240. Following are the state meaning and timing comments for the TRIG_IN signal. Note that TRIG_IN is an active-high (rising-edge triggered) signal.
Page 98: Memory Address Attributes (Maa[0:2])-Output
2.2.5.10.2 PCI Address Attributes (PMAA[0:2])—Output The memory attribute signals are associated with the PCI interface and provide information about the source of the PCI operation being performed by the MPC8240. They are also reset conﬁguration input signals. State Meaning Asserted/Negated—These signals are encoded to provide more...
Page 99: Memory Interface Valid (Miv)-Output
HRST_CPU and HRST_CTRL as part of the reset conﬁguration signals. See Section 2.4, “Conﬁguration Signals Sampled at Reset.” 2.2.6.2 JTAG Test Clock (TCK)—Input The JTAG test clock (TCK) signal is an input on the MPC8240. Following is the state meaning for the TCK input signal. State Meaning Asserted/Negated—This input should be driven by a free-running...
Page 100: Jtag Test Data Input (Tdi)-Input
TCK. The TDO signal remains in a high-impedance state except when scanning of data is in progress. 2.2.6.5 JTAG Test Mode Select (TMS)—Input The test mode select (TMS) signal is an input on the MPC8240. Following is the state meaning for the TMS input signal. State Meaning Asserted/Negated—This signal is decoded by the internal JTAG TAP...
Page 101: System Clock Input (Osc_In)-Input
Speciﬁcation for a complete listing of supported PLL_CFG[0:4] settings. 2.2.7.5 SDRAM Clock Outputs (SDRAM_CLK[0:3])—Output The MPC8240 provides four low-skew copies of the SDRAM clock for use in small memory subsystems. This clock is synchronized to the on-chip logic using a DLL. If these outputs are not needed, they can be individually disabled in the CDCR register to minimize power consumption.
Page 102: Debug Clock (Cko)-Output
Clocking 2.2.7.8 Debug Clock (CKO)—Output The debug clock (CKO) signal is an output on the MPC8240. The internal signal reﬂected on CKO is determined by either the HID0[ECLK,SBCLK] bits (if PMCR1[CKO_SEL] = 0), or the two-bit PMCR1[CKO_MODE] ﬁeld (if PMCR1[CKO_SEL] = 1).Both of these options allow the CKO output driver to be disabled.
Page 103: Dll Operation And Locking
SDRAM_SYNC_OUT should be fed back through a delay loop into the SDRAM_SYNC_IN input of the MPC8240. By adjusting the length of the delay loop, it is possible to remove the effects of trace delay to the system memory. This is accomplished when the delay through the loop is equivalent to the delay to the system memory.
Page 104: Clock Synchronization
PCI_SYNC_IN and the PLL_CFG[0:4] setting at reset. All of these clocks are synchronized by the internal logic of the MPC8240. In systems that use an external PLL to generate the memory system clocks and do not depend on the SDRAM_CLK[0:3] signals...
Page 105: Clocking System Solution Examples
2.3.4 Clocking System Solution Examples This section describes two example clocking solutions for different system requirements. For systems where the MPC8240 is the host controller with a minimum number of clock loads, clock fanout buffers are provided on-chip (shown in Figure 2-5). For systems requiring more clock fanout or where the MPC8240 is an agent device, external clock buffers may be used as shown in Figure 2-6.
Page 106: Configuration Signals Sampled At Reset
Table 2-5 contains a description of the signals sampled for conﬁguration at the negation of the HRST_CTRL and HRST_CPU signals. Note that throughout this manual, the reset conﬁguration signals are described as being sampled at the negation of reset. However, the 2-38 MPC8240 Integrated Processor User’s Manual...
Page 107: Mpc8240 Reset Configuration Signals
HRST_CTRL and HRST_CPU signals, as described in the MPC8240 Hardware Speciﬁcation. For more information about the timing requirements of these conﬁguration signals relative to the negation of the reset signals, refer to the MPC8240 Hardware Speciﬁcation. The reset conﬁguration signals serve multiple purposes, and the signal names do not reﬂect the functionality of the signals as they are used for reset conﬁguration.
Page 108 These ﬁve signals select the clock frequency ratios used by the two PLLs of the MPC8240. The value of PLL_CFG[0:4] during reset affects the read-only PLLRATIO driven ﬁeld stored in HID1. Note that system software cannot associate the PLLRATIO value with a unique PLL_CFG[0:4] value.The MPC8240 Hardware Speciﬁcation lists the...
Page 109: Address Maps
PCI host and the address map conﬁguration pin is pulled high, the MPC8240 uses address map B. If the MPC8240 is conﬁgured as a PCI agent, it must be conﬁgured to use address map B. In agent mode, the MPC8240 offers address translation capability to allow address remapping for inbound and outbound PCI memory transactions.
Page 110: Address Map B—Processor View In Host Mode
PCI memory device (host mode), a PCI memory device (agent mode), and a PCI I/O device, respectively. When conﬁgured for map B, the MPC8240 translates addresses across the internal peripheral logic bus and the external PCI bus as shown in Figure 3-1 through Figure 3-3.
Page 111: Address Map B—Pci Memory Master View In Agent Mode
64 Kbytes has been deﬁned (0xFE00_0000–0xFE00–FFFF). The processor address range 0xFE01_0000–0xFE7F_FFFF is reserved for future use. 5. The MPC8240 forwards processor transactions in this range to the PCI I/O space with the 8 most signiﬁcant bits cleared (that is, AD[31:0] = 0x00 || A[8:31]).
Page 112: Processor Core Address Map B In Host Mode
4GB - 18MB Access CONFIG_DATA Not addressable by 4GB - 17MB processor PCI Int Ack Int Ack Broadcast PCI 4GB - 16MB ROM or Flash ROM Access Figure 3-1. Processor Core Address Map B in Host Mode MPC8240 Integrated Processor User’s Manual...
Page 113: Pci Memory Master Address Map B In Host Mode
Address Map B PCI Master MPC8240 Memory Space MPC8240 Memory Controller Memory Space Local memory space Forwarded to local Local memory in 0 to 1GB memory Interface 0 to 1GB range. Memory controller performs memory cycles Memory select error Ignored.
Page 114: Pci I/O Master Address Map B
Not addressable by processor 16MB Addressable by local processor 1GB - 8MB MPC8240 does not respond as a target to PCI I/O accesses Not addressable by processor Figure 3-3. PCI I/O Master Address Map B MPC8240 Integrated Processor User’s Manual...
Page 115: Address Map B Options
Address Map B Options 3.2 Address Map B Options When conﬁgured for address map B and host mode, the MPC8240 supports four optional address mappings by programming the AMBOR register; see Section 4.9, “Address Map B Options Register—0xE0.” The options available are as follows: •...
Page 116: Address Map B—Processor View In Host Mode Options
2. If AMBOR[CPU_FD_ALIAS_EN] = 1 (see Section 4.9, “Address Map B Options Register—0xE0”), the MPC8240 forwards processor transactions in this range to the zero-based PCI memory space with the 8 most signiﬁcant bits cleared (that is, AD[31:0] = 0x00 || A[8:31] of the internal peripheral logic address bus).
Page 117: Pci Compatibility Hole And Alias Space
Address Map B Options Processor PCI Memory Space View Transactions in the processor compatibility hole are forwarded 640 KB 640 KB to PCI memory space Processor Processor Compatibility Hole Compatibility Hole 768 KB 768 KB 16 MB PCI memory space Transactions 4 GB - 48 MB in the alias space...
Page 118: Address Map B Pci Options In Host Mode
(that is, 0x00 || AD[23:0]). 3. The MPC8240 will respond to PCI memory cycles in the range PCSRBAR to PCSRBAR + 4 Kbytes (for runtime registers). PCSRBAR can be programmed to be anywhere from 0x8000_0000 – 0xFCFF_FFFF or from 0xFE00_0000 –...
Page 119: Address Translation
PCI (outbound) transactions. Note that address translation is supported only for agent mode; it is not supported when the MPC8240 is operating in host mode. Also note that since agent mode is supported only for address map B, address translation is supported only for address map B.
Page 120: Inbound Pci Address Translation
Translation Registers.” Inbound address translation may be disabled by programming the inbound window size in the ITWR to all zeros. If inbound translation is disabled, the MPC8240 ignores all PCI memory transactions. Note that overlapping the inbound memory window and the outbound translation window is not supported and can cause unpredictable behavior.
Page 121: Outbound Pci Address Translation
For outbound translation, an outbound memory window is speciﬁed in the upper 2 Gbytes of the MPC8240’s address space, and an outbound translation window is speciﬁed in the PCI memory space. Processor and DMA transactions that fall within the outbound memory window are forwarded to the PCI bus with the address translated to the outbound translation window.
Page 122: Address Translation Registers
Outbound EUMB—see Section 3.4, “Embedded Speciﬁes the starting address of the outbound translation window Utilities Memory Block (EUMB)” translation window and the size of the window. register Offset 0x0_2308 (local) (OTWR) Offset 0x308 (PCI) 3-14 MPC8240 Integrated Processor User’s Manual...
Page 123: Local Memory Base Address Register (Lmbar)
Note that the EUMB area must be selected ﬁrst, then the ITWR programmed, and then these bits can be set. 11–4 — All 0s Reserved; the MPC8240 only allows a minimum of a 4KByte window. Prefetchable Indicates that the space is prefetchable. 2–1 Type The inbound memory window may be located anywhere within the 32-bit PCI address space.
Page 124: Outbound Memory Base Address Register (Ombar)
The lower-order address bits of the base address ﬁeld of ITWR that are within the range speciﬁed by the window size are ignored and the MPC8240 ignores the incoming lower-order address bits (within the range speciﬁed by the window size). However, for future compatibility, it is recommended that the base address be programmed to be naturally aligned to the window size.
Page 125: Outbound Translation Window Register (Otwr)
Description Value — Reserved. The outbound memory window must reside in the upper 2 Gbytes of the MPC8240 address space. 30–12 Outbound Undeﬁned R/W Processor address that is the starting address for the outbound memory base memory window. The outbound memory window must be aligned address based on the granularity speciﬁed by the outbound window size...
Page 126: Embedded Utilities Memory Block (Eumb)
The lower-order address bits of the base address ﬁeld of OTWR that are within the range speciﬁed by the window size are ignored and the MPC8240 ignores the outgoing lower-order address bits (within the range speciﬁed by the window size). However, for future compatibility, it is recommended that the base address be programmed to be naturally aligned to the window size.
Page 127: Peripheral Control And Status Registers
— 3.4.2 Peripheral Control and Status Registers The MPC8240 contains a set of memory mapped registers that are accessible from the PCI bus in both host and agent mode. These registers allow external masters on the PCI bus to access the MPC8240’s on-chip embedded utilities such as the message unit, DMA Chapter 3.
Page 128: Embedded Utilities Memory Block Mapping To Pci Memory
0x400 – 0xEFF Reserved — 0xF00 – 0xF17 Data path diagnostics Section 15.1, “Debug Register Summary 0xF18 – 0xF48 Data path diagnostics Chapter 16, “Programmable I/O and Watchpoint (watchpoint registers) 0xF4D – 0xFFF Reserved — 3-20 MPC8240 Integrated Processor User’s Manual...
Page 129: Configuration Registers
All the conﬁguration registers of the MPC8240 are intrinsically little-endian. In the register descriptions of this chapter, bit 0 is the least signiﬁcant bit of the register.
Page 130: Configuration Register Access In Little-Endian Mode
A subset of the conﬁguration registers is accessible from the PCI bus through the use of PCI conﬁguration transactions. The MPC8240 responds to standard PCI conﬁguration transactions when its IDSEL signal is asserted. Table 4-3 provides a listing of conﬁguration registers accessible from the PCI bus.
Page 131: Configuration Register Access In Big-Endian Mode
Conﬁguration Register Access Code sequence: stw r0,0(r1) sync r3,2(r2) sync Results:Address 0xFEC0_0000 contains 0x8000_00A8 (MSB to LSB) Register at 0xA8 contains 0xFFDD_FFFF (AB to A8) Example: Map A conﬁguration sequence, 4-byte data write to register at address offset 0xA8 Initial values:r0 contains 0x8000_00A8 r1 contains 0x8000_0CF8 r2 contains 0xAABB_CCDD Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Page 132 0xAABB_CCDD r3 contains 0x8000_0CFC Register at 0xA8 contains 0xFFFF_FFFF (AB to A8) Code sequence: stwbrx r0,0,r1 sync sthbrx r2,0,r3 sync Results:Address 0x8000_0CF8 contains 0x8000_0004 (MSB to LSB) Register at 0xA8 contains 0xFFFF_CCDD (AB to A8) MPC8240 Integrated Processor User’s Manual...
Page 133: Configuration Register Summary
Table 4-2 describes the conﬁguration registers that are accessible by the processor core. Not all registers are shown in this document. Note that any conﬁguration addresses not deﬁned in Table 4-2 are reserved. Table 4-2. MPC8240 Configuration Registers Accessible from the Processor Core Program...
Page 134 Conﬁguration Register Access Table 4-2. MPC8240 Configuration Registers Accessible from the Processor Core (Continued) Program Address Register Size Access Access Reset Value Offset Size (Bytes) 0x0E Header type (not shown) 1 byte Read 0x00 0x0F BIST control 1 byte Read...
Page 135 Read/Write 0x0000_0000 0xFC MCCR4 4 bytes 1, 2, or 4 Read/Write 0x0000_0000 others Reserved — — — — Note: Reset values marked mode-dependent are deﬁned by whether the MPC8240 is operating in host or agent mode. Chapter 4. Conﬁguration Registers...
Page 136: Pci-Accessible Configuration Registers
Figure 4-1. Processor Accessible Configuration Space 4.1.3.2 PCI-Accessible Conﬁguration Registers Table 4-3 lists the subset of conﬁguration registers that are accessible from the PCI bus. Note that conﬁguration addresses not deﬁned in Table 4-3 are reserved. MPC8240 Integrated Processor User’s Manual...
Page 137: Mpc8240 Configuration Registers Accessible From The Pci Bus
MAX LAT 1-byte Read 0x00 0x46 PCI arbiter control register 2-bytes Read/Write 0x0000 Others Reserved — — — — Note: Reset values marked mode-dependent are deﬁned by whether the MPC8240 is operating in host or agent mode. Chapter 4. Conﬁguration Registers...
Page 138: Pci Interface Configuration Registers
4.2 PCI Interface Conﬁguration Registers The PCI Local Bus Speciﬁcation deﬁnes the conﬁguration registers from 0x00 through 0x3F. Table 4-4 summarizes the PCI conﬁguration registers of the MPC8240. Detailed descriptions of these registers are provided in the PCI Local Bus Speciﬁcation.
Page 139: Pci Command Register-Offset 0X04
To do this, the conﬁguration software must read the vendor id in each possible PCI slot. If there is no response to a read of an empty slot, the MPC8240 returns 0xFFFF (the invalid vendor id). Any conﬁguration write cycle to a reserved register is completed normally and the data is discarded.
Page 140: Pci Status Register-Offset 0X06
— All 0s These bits are reserved. Fast back-to-back This bit is hardwired to 0, indicating that the MPC8240 does not run fast back-to-back transactions. SERR This bit controls the SERR driver of the MPC8240. This bit (and bit 6) must be set to report address parity errors.
Page 141: Pci Status Register—0X06
• Bit 6 (parity error response) in the PCI command register was set. Fast back-to-back This bit is hardwired to 1, indicating that the MPC8240 (as a target) is capable capable of accepting fast back-to-back transactions. —...
Page 142: Programming Interface-Offset 0X09
Mode- 0x06 When MPC8240 is conﬁgured as a host bridge to indicate “Host Bridge.” dependent 0x0E When MPC8240 is conﬁgured as a target device to indicate the device is an agent and is I O capable. 4.2.5 PCI Cache Line Size—Offset 0x0C Table 4-9 describes the processor cache line size register (PCLSR).
Page 143: Pci Base Address Registers-Lmbar And Pcsrbar
These registers allow a host processor to conﬁgure the base addresses of the MPC8240 when the MPC8240 is being used as a PCI agent. The use of these memory spaces is optional and therefore selectable by the processor. It is expected that the processor core conﬁgures the local memory and enables the embedded utilities prior to the host software...
Page 144: Pci Interrupt Line-Offset 0X3C
Value Enable on-chip PCI arbitration 0 If cleared, the on-chip arbiter for external PCI masters is disabled, and the MPC8240 presents its request on GNT0 to the external arbiter and receives its grant on REQ0. 1 If set, indicates the on-chip arbiter is enabled.
Page 145: Peripheral Logic Power Management Configuration Registers (Pmcrs)
Value NO_NAP_MSG HALT command broadcast—Not supported on the MPC8240. 1 Initialization software must set this bit, indicating that the MPC8240 does not broadcast a HALT command on the PCI bus before entering the nap mode. NO_SLEEP_MSG Sleep message broadcast.—Not supported on the MPC8240.
Page 146 1 Enables the peripheral logic power management logic within the MPC8240 — Reserved DOZE Enables/disables the doze mode capability of the MPC8240. Note that this bit is only valid if MPC8240 power management is enabled. (PMCR1[PM] = 1). 0 Disables the doze mode 1 Enables the doze mode Enables/disables the nap mode capability of the MPC8240.
Page 147: Power Management Configuration Register 2 (Pmcr2)—0X72
DLL_EXTEND This bit can be used to shift the lock-range of the DLL by half of a PCI clock cycle. See the MPC8240 Hardware Speciﬁcation for more information on the use of the DLL extend feature. 0 DLL extended range 1 Standard (non-extended) range 6–4...
Page 148: Output/Clock Driver And Miscellaneous I/O Control Registers
4.4 Output/Clock Driver and Miscellaneous I/O Control Registers Table 4-17 describes the general output driver control available with the MPC8240 through the output driver control register (ODCR), and Table 4-18 describes the output enable/disable capability available for the clock signals through the clock driver control register (CDCR).
Page 149 Output/Clock Driver and Miscellaneous I/O Control Registers Table 4-17. Output Driver Control Register Bit Definitions—0x73 (Continued) Reset Bits Name Description Value DRV_MEM_CTRL_2 Driver capability for address signals (RAS/CS[0:7], CAS/DQM[0:7], WE, FOE, RCS0, SDBA0, AR[19:12], SDRAS, SDCAS, CKE, AS, SDMA[12:0]). The meaning of this bit setting depends on the setting of DRV_MEM_CTRL_1.
Page 150: Embedded Utilities Memory Block Base Address Register-0X78
4.5 Embedded Utilities Memory Block Base Address Register—0x78 The embedded utilities memory block base address register (EUMBBAR), shown in Table 4-19, controls the placement of the embedded utilities memory block (EUMB). See Section 3.4, “Embedded Utilities Memory Block (EUMB).” 4-22 MPC8240 Integrated Processor User’s Manual...
Page 151: Memory Interface Configuration Registers
(starting and ending addresses), memory bank enables, memory timing, and external memory buffers. Initialization software must program the MICRs at reset and then enable the memory interface on the MPC8240 by setting the MEMGO bit in memory control conﬁguration register 1 (MCCR1).
Page 152: Memory Starting Address Register 2—0X84
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 25 24 23 18 17 16 15 10 9 Figure 4-10. Extended Memory Starting Address Register 2—0x8C 4-24 MPC8240 Integrated Processor User’s Manual...
Page 153: Memory Ending Address Register 1—0X90
Memory Interface Conﬁguration Registers Table 4-21. Bit Settings for Extended Memory Starting Address Registers 1 and 2 Bits Name Reset Value Description Byte Address 31–26 — All 0s Reserved 0x88 25–24 Extended starting address 3 0b00 Extended starting address for bank 3 23–18 —...
Page 154: Extended Memory Ending Address Register 1—0X98
15–10 — All 0s Reserved 9–8 Extended ending address 1 0b00 Extended ending address for bank 1 7–2 — All 0s Reserved 1–0 Extended ending address 0 0b00 Extended ending address for bank 0 4-26 MPC8240 Integrated Processor User’s Manual...
Page 155: Memory Bank Enable Register-0Xa0
Memory Interface Conﬁguration Registers Table 4-23. Bit Settings for Extended Memory Ending Address Registers 1 and 2 Reset Bits Name Description Byte Address Value 31–26 — All 0s Reserved 0x9C 25–24 Extended ending address 7 0b00 Extended ending address for bank 7 23–18 —...
Page 156: Memory Page Mode Register-0Xa3
The 1-byte memory page mode register, shown in Figure 4-16 and Table 4-25, contains the PGMAX parameter which controls how long the MPC8240 retains the currently accessed page (row) in memory. See Section 6.3.7, “FPM or EDO DRAM Page Mode Retention,” or Section 6.2.7, “SDRAM Page Mode,”...
Page 157: Processor Interface Configuration Registers
Processor Interface Conﬁguration Registers 4.7 Processor Interface Conﬁguration Registers The processor interface conﬁguration registers (PICRs) control the programmable parameters of the peripheral bus interface to the processor core. There are two 32-bit PICRs—PICR1 and PICR2. Figure 4-17 shows the bits of PICR1. Reserved Speculative PCI Reads CF_APARK...
Page 158 ADDRESS_MAP Address map. This bit controls which address map is used by the MPC8240. The initial state of this bit is determined by the inverse of the address map conﬁguration signal (MAA0) during reset.Software that dynamically changes this bit must ensure that there are no pending PCI transactions and that there is a sync instruction following the address map change to allow the update to take effect.
Page 159: Processor Interface Configuration Register 2 (Picr2)—0Xac
Table 4-26. Bit Settings for PICR1—0xA8 (Continued) Reset Bits Name Description Value LE_MODE This bit controls the endian mode of the MPC8240. See Appendix B, “Bit and Byte Ordering,” for more information. 0 Big-endian mode 1 Little-endian mode — Reserved and must be set CF_APARK This bit indicates whether the processor address bus is parked.
Page 160: Bit Settings For Picr2—0Xac
Flash write lockout. This bit, once set, prevents writing to Flash. Once set, this bit can only be cleared by a hard reset. 0 Write operations to Flash are enabled, provided FLASH_WR_EN = 1. 1 Write operations to Flash are disabled until the MPC8240 is reset. 24–20 — 0_0000 Reserved 19–18...
Page 161: Error Handling Registers
ECC single-bit error trigger register, then an error is reported (provided ErrEnR1[2] = 1). The ECC single-bit error trigger, shown in Figure 4-20, provides a threshold value that, when equal to the single-bit error count, triggers the MPC8240 error reporting logic. Chapter 4. Conﬁguration Registers 4-33...
Page 162: Error Enabling And Detection Registers
ErrEnR2. The error detection registers 1 and 2 (ErrDR1 and ErrDR2), shown in Figure 4-22 and Figure 4-25, contain error ﬂags that report when the MPC8240 detects a speciﬁc error condition. The error detection registers are bit-reset type registers. That is, reading from these registers occurs normally;...
Page 163: Error Enabling Register 1 (Errenr1)—0Xc0
1 Received PCI SERR enabled PCI target PERR This bit enables the reporting of data parity errors on the PCI bus for enable transactions involving the MPC8240 as a target. 0 Target PERR disabled 1 Target PERR enabled Memory select error...
Page 164: Error Detection Register 1 (Errdr1)—0Xc1
1 SERR detected PCI target PERR PCI target PERR 0 The MPC8240, as a PCI target, has not detected a data parity error 1 The MPC8240, as a PCI target, detected a data parity error Memory select error Memory select error...
Page 165: Internal Processor Bus Error Status Register—0Xc3
Error Handling Registers Table 4-31. Bit Settings for Error Detection Register 1 (ErrDR1)—0xC1 (Continued) Reset Bits Name Description Value Memory read parity Memory read parity error/ECC single-bit error trigger exceeded error/ECC single-bit 0 No error detected error trigger exceeded 1 Parity error detected or ECC single-bit error trigger exceeded 1–0 Unsupported Unsupported processor transaction...
Page 166: Bit Settings For Error Enabling Register 2 (Errenr2)—0Xc4
PCI address parity This bit controls whether the MPC8240 asserts MCP (provided MCP is error enable enabled) if an address parity error is detected by the MPC8240 acting as a PCI target. 0 PCI address parity errors disabled 1 PCI address parity errors enabled 6–4...
Page 167: Error Detection Register 2 (Errdr2)—0Xc5
Flash ROM write error Flash ROM write error 0 No error detected 1 The MPC8240 detected a write to Flash ROM when writes to ROM/Flash are disabled. The PCI bus error status register latches the state of the PCI C/BE[3:0] signals when an error is detected on the PCI bus as deﬁned in Section 13.3.3, “PCI Interface Errors.”...
Page 168: Pci Bus Error Status Register—0Xc7
7–5 — Reserved MPC8240 MPC8240 master/target status master/target status 0 MPC8240 is the PCI master. 1 MPC8240 is the PCI target. 3–0 C/BE[3:0] 0000 These bits maintain a copy of C/BE[3:0]. When a PCI bus error is detected, these bits are latched until all error ﬂags are cleared.
Page 169: Address Map B Options Register-0Xe0
0xFDxx_xxxx. This bit is used only for address map B (and not supported in agent mode). 0 No response 1 The MPC8240, as a PCI target, responds to addresses in the range 0xFD00_0000–0xFDFF_FFFF (asserts DEVSEL), and forwards the transaction to system memory as 0x0000_0000–0x00FF_FFFF.
Page 170: Memory Control Configuration Registers
The four 32-bit memory control conﬁguration registers (MCCRs) set all RAM and ROM parameters. These registers are programmed by initialization software to adapt the MPC8240 to the speciﬁc memory organization used in the system. After all the memory conﬁguration parameters have been properly conﬁgured, the initialization software turns on the memory interface using the MEMGO bit in MCCR1.
Page 171 Memory Control Conﬁguration Registers Bank 7 Row Bank 6 Row Bank 5 Row PCKEN Bank 4 Row RAM_TYPE Bank 3 Row SREN Bank 2 Row MEMGO Bank 1 Row BURST Bank 0 DBUS_SIZ[0–1] ROMNAL ROMFAL 28 27 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Figure 4-29.
Page 172 RAM interface logic enable. Note that this bit must not be set until all other memory conﬁguration parameters have been appropriately conﬁgured by boot code. 0 MPC8240 RAM interface logic disabled 1 MPC8240 RAM interface logic enabled SREN Self-refresh enable. Note that if self refresh is disabled, the system is responsible for preserving the integrity of DRAM/EDO/SDRAM during sleep mode.
Page 173: Memory Control Configuration Register 2 (Mccr2)—0Xf4
Memory Control Conﬁguration Registers Table 4-38. Bit Settings for MCCR1—0xF0 (Continued) Reset Bits Name Description Value 9–8 Bank 4 row RAM bank 4 row address bit count. See the description for Bank 7 row (bits 15–14). 7–6 Bank 3 row RAM bank 3 row address bit count.
Page 174: Bit Settings For Mccr2—0Xf4
AS fall time. These bits control the falling edge timing of the AS signal for the Port X interface. See Section 6.4.7, “Port X Interface,” for more information. 0000 0 clocks (AS asserted coincident with the chip select) 0001 1 clock 0010 2 clocks 0011 3 clocks 1111 15 clocks 4-46 MPC8240 Integrated Processor User’s Manual...
Page 175 0 MPC8240 uses ECC on the memory data bus. 1 MPC8240 uses parity on the memory data bus. WRITE_ Write parity check enable. This bit controls whether the MPC8240 uses the parity PARITY_ checking hardware in the data path to report peripheral bus parity errors on memory system write operations.
Page 176: Memory Control Configuration Register 3 (Mccr3)—0Xf8
RSV_PG Reserve page register. If this bit is set, the MPC8240 reserves one of the four page registers at all times. This is equivalent to only allowing three simultaneous open pages.
Page 177: Bit Settings For Mccr3—0Xf8
Memory Control Conﬁguration Registers Table 4-40. Bit Settings for MCCR3—0xF8 Reset Bits Name Description Value 31–28 BSTOPRE[2–5] 0000 Burst to precharge—bits 2–5. For SDRAM only. These bits, together with BSTOPRE[0–1] (bits 19–18 of MCCR4), and BSTOPRE[6–9] (bits 3–0 of MCCR4), control the open page interval. The page open duration counter is reloaded with BSTOPRE[0–9] every time the page is accessed (including page hits).
Page 178 DRAMs used and the frequency of the memory interface. See Section 6.3.5, “FPM or EDO DRAM Interface Timing,” for more information. 001 1 clock 010 2 clocks 011 3 clocks 111 7 clocks 000 8 clocks 4-50 MPC8240 Integrated Processor User’s Manual...
Page 179: Memory Control Configuration Register 4 (Mccr4)—0Xfc
Memory Control Conﬁguration Registers Table 4-40. Bit Settings for MCCR3—0xF8 (Continued) Reset Bits Name Description Value 5–3 RAS to CAS delay interval. For DRAM/EDO only. These bits control the number of clock cycles between the assertion of RAS and the ﬁrst assertion of CAS.
Page 180: Bit Settings For Mccr4—0Xfc
10 In-line buffer mode; SDRAM only 11 Reserved The MPC8240 must be conﬁgured for in-line buffer mode in order to use the in-line ECC/parity logic for SDRAM. The in-line ECC and parity hardware allow the MPC8240 to check/generate parity on the internal peripheral logic bus and check/correct/generate ECC or parity on the external SDRAM memory bus.
Page 181 SDRAM array during power-up conﬁguration. Note that the SDRAM mode register ‘opcode’ ﬁeld is not speciﬁed and is forced to b’0_0000’ by the MPC8240 when the mode registers are written. Bits 14–12 CAS latency...
Page 182 MCCR3), control the open page interval. The page open duration counter is reloaded with BSTOPRE[0–9] every time the page is accessed (including page hits). When the counter expires, the open page is closed with a SDRAM-precharge bank command. See Chapter 6, “MPC8240 Memory Interface,” for more information. 4-54...
Page 183: Powerpc Processor Core
Chapter 5 PowerPC Processor Core The MPC8240 contains an embedded version of the PowerPC 603e™ processor called the processor core. This chapter provides an overview of the basic functionality of the processor core. For detailed information regarding the processor refer to the following: •...
Page 184: Mpc8240 Integrated Processor Core Block Diagram
16-Kbyte 16-Kbyte Tags Tags JTAG/COP Clock D Cache I Cache Interface Multiplier Touch Load Buffer PERIPHERAL LOGIC BUS INTERFACE Copyback Buffer 32-BIT ADDRESS BUS 32-/64-BIT DATA BUS Figure 5-1. MPC8240 Integrated Processor Core Block Diagram MPC8240 Integrated Processor User’s Manual...
Page 185: Powerpc Processor Core Features
TLB and BAT array, the BAT translation takes priority. As an added feature to the MPC603e core, the MPC8240 can lock the contents of 1–3 ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache.
Page 186 — A 64-entry, two-way set-associative DTLB — Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks — Software table search operations and updates supported through fast trap mechanism — 52-bit virtual address; 32-bit physical address MPC8240 Integrated Processor User’s Manual...
Page 187: Instruction Unit
— Support for one-level address pipelining and out-of-order bus transactions — Hardware support for misaligned little-endian accesses — Coﬁgurable processor bus frequency multipliers as deﬁned in the MPC8240 Integrated Processor Hardware Speciﬁcations. • Integrated power management — Three power-saving modes: doze, nap, and sleep —...
Page 188: Instruction Queue And Dispatch Unit
GPRs or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches. In addition to the BPU, the processor core provides four other execution units and a completion unit, which are described in the following sections. MPC8240 Integrated Processor User’s Manual...
Page 189: Integer Unit (Iu)
PowerPC Processor Core Features 5.2.4.1 Integer Unit (IU) The IU executes all integer instructions. The IU executes one integer instruction at a time, performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose registers are provided to support integer operations.
Page 190: System Register Unit (Sru)
The LSU calculates effective addresses for data loads and stores, performs data alignment to and from cache memory, and provides the sequencing for load and store string and multiple word instructions. The instruction unit calculates the effective addresses for instruction fetching. MPC8240 Integrated Processor User’s Manual...
Page 191: Cache Units
This internal bus is very similar in function to the external 60x bus interface on the MPC603e. In the case of the MPC8240, the central control unit (CCU) terminates all the transactions and internally directs all accesses to the appropriate peripheral (or memory) interface.
Page 192: Peripheral Logic Bus Frequency
PowerPC architecture—the user instruction set architecture (UISA), the virtual environment architecture (VEA), and the operating environment architecture (OEA), as well as the MPC8240 core implementation-speciﬁc registers. Full descriptions of the basic register set deﬁned by the PowerPC architecture are provided in Chapter 2, “PowerPC Register Set,”...
Page 193: Powerpc Register Set
Data is transferred between memory and registers with explicit load and store instructions only. Figure 5-2 shows the complete MPC8240 register set and the programming environment to which each register belongs. This ﬁgure includes both the PowerPC register set and the MPC8240-speciﬁc registers.
Page 194: Mpc8240 Programming Model—Registers
TBR 269 Instruction Address External Access Breakpoint Register Register (Optional) IABR SPR 1010 SPR 282 These implementation–specific registers may not be supported by other PowerPC processors or processor cores. Figure 5-2. MPC8240 Programming Model—Registers 5-12 MPC8240 Integrated Processor User’s Manual...
Page 195: Mpc8240-Specific Registers
5.3.1.2 MPC8240-Speciﬁc Registers The set of registers speciﬁc to the MPC603e are shown in Figure 5-2. Most of these are described in the MPC603e User’s Manual and are implemented in the MPC8240 as follows: • MMU software table search registers—DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA.
Page 196 In nap mode, the PLL and the time base remain active. Note that the MPC8240 asserts the QACK output signal depending on the power-saving state of the peripheral logic, and not on the power-saving state of the processor core.
Page 197 Programming Model Table 5-1. HID0 Field Descriptions (Continued) Bits Name Description Instruction cache enable 0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and cache operations) are ignored.
Page 198: Hardware Implementation-Dependent Register 1 (Hid1)
Table 5-1. HID0 Field Descriptions (Continued) Bits Name Description — IFEM bit on some other PowerPC devices This bit is not used in the MPC8240 (and so it is reserved). 25–26 — Reserved FBIOB Force branch indirect on bus 0 Register indirect branch targets are fetched normally 1 Forces register indirect branch targets to be fetched externally.
Page 199: Hardware Implementation-Dependent Register 2 (Hid2)
PLL_CFG[0–4] signals during reset and the processor-to-memory clock frequency ratio deﬁned by that PLL_CFG[0–4] value. See MPC8240 Hardware Speciﬁcation for a listing of supported settings. Note that multiple settings of the PLL_CFG[0–4] signals can map to the same PLLRATIO value.
Page 200: Powerpc Instruction Set And Addressing Modes
Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations. In addition to the functionality of the MPC603e, the MPC8240 has additional hardware support for misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian load/store accesses not on a word boundary generate exceptions under the same circumstances as big-endian requests.
Page 201 Programming Model — Floating-point compare — Floating-point status and control • Load/store instructions—These include integer and ﬂoating-point load and store instructions. — Integer load and store — Integer load and store with byte reverse — Integer load and store string/multiple —...
Page 202: Cache Implementation
— External Control In Word Indexed (eciwx) — External Control Out Word Indexed (ecowx) The MPC8240 does not provide the hardware support for misaligned eciwx and ecowx instructions provided by the MPC603e processor. An alignment exception is taken if these instructions are not word-aligned.
Page 203: Data Cache
MEI (modiﬁed/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC architecture deﬁnes the term ‘block’ as the cacheable unit. For the MPC8240’s processor core, the block size is equivalent to a cache line. Chapter 5. PowerPC Processor Core...
Page 204: Data Cache Organization
(except when a dependency exists, or in cases where a non-cacheable access is performed), and provides support for a write operation to proceed a previously queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data 5-22 MPC8240 Integrated Processor User’s Manual...
Page 205: Instruction Cache
Cache Implementation tenures of a read operation). Because the processor can dynamically optimize run-time ordering of load/store trafﬁc, overall performance is improved. 5.4.2.2 Instruction Cache The instruction cache also consists of 128 sets of four blocks—each block consists of 32 bytes, an address tag, and a valid bit.
Page 206: Cache Coherency
5.4.3 Cache Coherency The central control unit (CCU) manages the cache coherency within the MPC8240. It responds to all accesses generated by the processor core and causes the snooping of the addresses in the internal buffers as necessary. Also, the CCU generates snoop transactions on the peripheral logic bus to allow the processor to snoop accesses between the PCI interface and memory.
Page 207: Processor Responses To Pci-To-Memory Transactions
Table 5-5. CCU Responses to Processor Transactions (Continued) Processor Transaction CCU Response stwcx., reservation set CCU takes no further action. (The MPC8240 does not support atomic references in PCI memory space.) tlbsync CCU takes no further action. Graphic write (ecowx) Processor transaction error.
Page 208: Exception Model
If, for example, a single instruction encounters multiple exception conditions, those conditions are handled sequentially. After the exception handler handles an exception, the instruction execution continues until the next exception condition 5-26 MPC8240 Integrated Processor User’s Manual...
Page 209 All exceptions report recoverability through MSR[RI]. 5.5.2 MPC8240 Implementation-Speciﬁc Exception Model As speciﬁed by the PowerPC architecture, all processor core exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of which are maskable) are caused by events external to the processor’s...
Page 210: Exception Classifications For The Processor Core
HID0[EMCP] is set, PICR1[MCP_EN] is set, and MSR[ME] is set. When one of these errors occurs, the MPC8240 takes the exception and asserts the MCP output signal.
Page 211 Exception Model Table 5-8. Exceptions and Conditions (Continued) Exception Vector Offset Causing Conditions Type (hex) Alignment 00600 An alignment exception is caused when the processor core cannot perform a memory access for any of the reasons described below: • •The operand of a ﬂoating-point load or store is to a direct-store segment. •...
Page 212: Exception Priorities
4. A multiple or string access is attempted with MSR[LE] set. Also, there is a priority mechanism for all the conditions speciﬁc to the MPC8240 that can cause a machine check exception. These are described in Chapter 13, “Error Handling.”...
Page 213 TLB with memory. In the MPC8240, the processor core’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The MPC8240’s core provides hardware assist for software table search operations through the hashed page table on TLB misses.
Page 214: Instruction Timing
Instruction Timing The MPC8240 TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The processor core provides hardware assist for software table search operations through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.
Page 215: Integer Divide Latency
Instruction Timing • The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch. Additionally, the BPU decodes branches during the fetch stage and folds out branch instructions before the dispatch stage if possible. •...
Page 216: Differences Between The Mpc8240 Core And The Powerpc 603E Microprocessor
5.8 Differences between the MPC8240 Core and the PowerPC 603e Microprocessor The MPC8240 processor core is a derivative of the MPC603e microprocessor design. Some changes have been made and are visible either to a programmer or a system designer. Any software designed for an MPC603e is functional when replaced with the MPC8240 except for the speciﬁc customer-visible changes listed in Table 5-10.
Page 217 Differences between the MPC8240 Core and the PowerPC 603e Microprocessor Table 5-10. Major Differences between MPC8240’s Core and the MPC603e User’s Manual (Continued) Description Impact Areas of memory accessed by dcbz This was previously documented as an anomaly in the MPC603e. Areas of...
Page 218 Differences between the MPC8240 Core and the PowerPC 603e Microprocessor 5-36 MPC8240 Integrated Processor User’s Manual...
Page 219 Chapter 6 MPC8240 Memory Interface The MPC8240 integrates a high-performance memory controller that controls processor and PCI interactions to local memory. The MPC8240 supports various types of DRAM and ROM/Flash conﬁgurations as local memory. • SDRAM — SDRAMs must comply with the JEDEC speciﬁcation for SDRAM —...
Page 220 — SDRAM ECC—Located in-line with the data path buffers The MPC8240 is designed to control a 32- or 64-bit data path to main memory (SDRAM or DRAM). The MPC8240 can be conﬁgured to check parity or ECC on memory reads.
Page 221: Memory Interface Signal Summary
Figure 6-1. Block Diagram for Memory Interface 6.1 Memory Interface Signal Summary Table 6-1 summarizes the memory interface signals. Note that some signals function differently depending on the type of memory system the MPC8240 is conﬁgured to support. Table 6-1. Memory Interface Signal Summary Signal Name...
Page 222 Address strobe for Port X — The MPC8240 samples these signals at the negation of HRST_CTRL to determine the reset conﬁguration. After they are sampled, they assume their normal functions. See Section 2.4, “Conﬁguration Signals Sampled at Reset,” for more information about their function during reset.
Page 223: Memory Address Signal Mappings
SDMA10 SDMA10 AR10 AR10 A10(AP) SDMA9 SDMA9 SDMA9 SDMA8 SDMA8 SDMA8 SDMA7 SDMA7 SDMA7 SDMA6 SDMA6 SDMA6 SDMA5 SDMA5 SDMA5 SDMA4 SDMA4 SDMA4 SDMA3 SDMA3 SDMA3 SDMA2 SDMA2 SDMA2 SDMA1 SDMA1 SDMA1 SDMA0 SDMA0 SDMA0 Chapter 6. MPC8240 Memory Interface...
Page 224: Sdram Interface Operation
SDRAM Interface Operation 6.2 SDRAM Interface Operation Figure 6-2 shows an internal block diagram of the SDRAM interface of the MPC8240. SDRAM Memory Interface SDRAM Address Address SDRAM Memory Array (Processor or PCI) SDMA[12:0] SDBA[1:0] SDRAM Central Control Unit SDRAM Memory Control...
Page 225: Sdram Data Bus Lane Assignments
ﬁrst beat of write data is supplied concurrent with the write command. The memory design must be byte-selectable for writes using the MPC8240’s DQM outputs. The MPC8240 allows four simultaneous open pages for page mode; the number of clocks for which the pages are maintained open is programmable by the BSTOPRE and PGMAX parameters.
Page 226: Example 512-Mbyte Sdram Configuration With Parity
3. Each of the CS[0:7] signals correspond with a separate physical bank of memory; CS0 for the first bank, etc. 4. Buffering may be needed if large memory arrays are used. 5. SDRAM_CLK[0:3] signals may be apportioned among all memory devices. Figure 6-3. Example 512-MByte SDRAM Configuration With Parity MPC8240 Integrated Processor User’s Manual...
Page 227: Supported Sdram Organizations
SDRAM banks may be implemented with memory devices requiring fewer than 28 address bits. The MPC8240 can be conﬁgured to provide 12- or 11-row bits to a particular bank, and 10, 9, 8, or 7 column bits, and 2 or 4 logical banks.
Page 228: Sdram Address Multiplexing
(4 banks) A logical bank is deﬁned for the MPC8240 as a portion of memory addressed through an SDRAM bank select. A physical bank is deﬁned for the MPC8240 as a portion of memory addressed through an SDRAM chip select.
Page 229 Table 6-7 shows the multiplexing of the internal physical addresses A[0 ] through SDBA[1:0] and SDMA[12:0] during the row and column phases of the 64-bit mode. The shaded cells in Figure 6-7 are the unspeciﬁed bits. Chapter 6. MPC8240 Memory Interface 6-11...
Page 230 9 8 7 6 5 4 3 2 1 0 SDCAS 7 6 5 4 3 2 1 0 12x9x4 SDRAS 9 8 7 6 5 4 3 2 1 0 SDCAS 7 6 5 4 3 2 1 0 6-12 MPC8240 Integrated Processor User’s Manual...
Page 231: Sdram Memory Data Interface
7 6 5 4 3 2 1 0 6.2.3 SDRAM Memory Data Interface To reduce loading on the data bus, the MPC8240 features on-chip buffers between the internal processor core data bus and the memory data bus. The MPC8240 supports three types of internal data path buffering for the SDRAM data interface—ﬂow-through,...
Page 232: Sdram Flow-Through Memory Interface
Figure 6-4. SDRAM Flow-Through Memory Interface The registered buffer mode interface is shown in Figure 6-5. The registered buffer mode allows a higher memory interface frequency at the expense of a clock cycle of latency on SDRAM reads. 6-14 MPC8240 Integrated Processor User’s Manual...
Page 233: Sdram Registered Memory Interface
Internal Bus Clock collect Data Signals Error signals to Peripheral Logic error signals SDRAM data path Parity Check Internal Data to SDRAM ECC or Parity Generate Output enable Figure 6-6. . SDRAM In-line ECC/Parity Memory Interface Chapter 6. MPC8240 Memory Interface 6-15...
Page 234: Sdram Power-On Initialization
• BUF_TYPE—selects the data path buffer mode (ﬂow-through, registered, in-line) • REGDIMM—enables registered DIMM mode • SDMODE—mode register data to be transferred to SDRAM array by the MPC8240 —speciﬁes CAS latency, wrap type, and burst length • ACTORW—activate to read or write interval 6-16 MPC8240 Integrated Processor User’s Manual...
Page 235: Mpc8240 Interface Functionality For Jedec Sdrams
When the sequence completes, the SDRAM array is ready for access. 6.2.5 MPC8240 Interface Functionality for JEDEC SDRAMs All read or write accesses to SDRAM are performed by the MPC8240 using various combinations of the JEDEC standard SDRAM interface commands. SDRAM samples command and data inputs on rising edges of the memory clock.
Page 236: Sdram Burst And Single-Beat Transactions
— Although some SDRAMs provide variable burst lengths of 1, 2, 4, 8 page size, the MPC8240 supports only a burst length of 4 or 8. Burst length 4 must be selected for operation with a 64 bit memory interface and 8-beat burst lengths are used with a 32-bit memory interface.
Page 237: Sdram Page Mode
SDRAM Interface Operation from memory in the order 2-3-0-1. In 32-bit data bus mode, if the processor core requests the third double word of a cache block, the MPC8240 reads words from memory in the order 4-5-6-7-0-1-2-3. For single-beat read transactions, the MPC8240 masks the extraneous data in the burst by driving the DQM[0:7] signals high on the irrelevant cycles.
Page 238: Pgmax Parameter Setting For Sdram Interface
ROM. If ROM is located on the PCI bus, the longest memory access is a burst read from the SDRAM. The MPC8240 also requires two clock cycles to issue a precharge bank command to the SDRAM device so the PGMAX interval must be further reduced by two clock cycles.
Page 239: Sdram Paging In Sleep Mode
6.2.8 SDRAM Interface Timing To accommodate available memory technology across a wide spectrum of operating frequencies, the MPC8240 allows the following SDRAM interface timing intervals to be programmable with granularity of 1 memory clock cycle: • RDLAT—internal processor core bus data latency from read command •...
Page 240: Sdram Interface Timing Intervals
The value of the above six parameters, (in whole clock cycles) must be set by boot code at system start-up and kept in the MPC8240 conﬁguration register space. The following ﬁgures show SDRAM timing for various types of accesses. Figure 6-8 shows a single-beat read operation.
Page 241: Sdram Single-Beat Read Timing (Sdram Burst Length = 4)
Figure 6-8. SDRAM Single-Beat Read Timing (SDRAM Burst Length = 4) Figure 6-9 shows a four-beat burst read operation. SDRAM CLK[0:3] SDRAS SDCAS ADDR ACTORW CAS latency DQM[0:7] D0 D1 D2 D3 DATA Read Figure 6-9. SDRAM Four-Beat Burst Read Timing Configuration—64-Bit Mode Chapter 6. MPC8240 Memory Interface 6-23...
Page 242: Sdram Eight-Beat Burst Read Timing Configuration—32-Bit Mode
Figure 6-10. SDRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode Figure 6-11 shows a single-beat write operation. SDRAM CLK[0:3] SDRAS SDCAS ADDR ACTORW DQM[0:7] DATA Write Figure 6-11. SDRAM Single Beat Write Timing (SDRAM Burst Length = 4) 6-24 MPC8240 Integrated Processor User’s Manual...
Page 243: Sdram Four-Beat Burst Write Timing—64-Bit Mode
Figure 6-12. SDRAM Four-Beat Burst Write Timing—64-Bit Mode SDRAM CLK[0:3] SDRAS SDCAS ADDR ACTORW DQM[0:7] DATA D0 D1 D2 D3 D4 D5 D6 D7 Write DQM and data latency = 0 for writes Figure 6-13. SDRAM Eight-Beat Burst Write Timing—32-Bit Mode Chapter 6. MPC8240 Memory Interface 6-25...
Page 244: Sdram Mode-Set Command Timing
SDRAM Interface Operation 6.2.8.1 SDRAM Mode-Set Command Timing The MPC8240 transfers the mode register data, (CAS latency, burst length, and burst type) stored in MCCR4[SDMODE] to the SDRAM array by issuing the mode-set command when MCCR1[MEMGO] is set. The timing of the mode-set command is shown in Figure 6-14.
Page 245: Rmw Parity Latency Considerations
(checking parity), and then merges that double word with the write data from the processor. The MPC8240 then generates new parity bits for the merged double word and writes the data and parity to memory. The read-modify-write process adds six clock cycles to a single-beat write operation.
Page 246: The Mpc8240 Sdram Ecc Syndrome Encoding (Data Bits 0:31)
Table 6-8 and Table 6-9 describe the conﬁguration requirements for this mode. The in-line ECC logic in the MPC8240 detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble. Other errors are not guaranteed to be detected or corrected.
Page 247: Sdram Registered Dimm Mode
DIMMs latch the SDRAM control signals internally before using them to access the array. Enabling the MPC8240’s registered DIMM mode (MCCR4 bit 15, REGDIMM = 1) compensates for this delay on the DIMMs control bus by delaying the MPC8240’s data and parity buses for SDRAM writes by one additional clock cycle.
Page 248: Registered Sdram Dimm Single-Beat Write Timing
Figure 6-15. Registered SDRAM DIMM Single-Beat Write Timing Figure 6-16 shows the registered SDRAM DIMM burst-write timing. SDRAM CLK[0:3] SDRAS SDCAS ADDR ACTORW DQM[0:7] DATA D0 D1 D2 D3 Write Figure 6-16. Registered SDRAM DIMM Burst-Write Timing 6-30 MPC8240 Integrated Processor User’s Manual...
Page 249: Sdram Refresh
MCCR2[REFINT]. REFINT is the refresh interval. When REFINT expires and the memory bus is idle, the MPC8240 issues a precharge and then a refresh command to the SDRAM devices. However, if the memory bus is busy with a transaction, the refresh request is not performed and an internal, 4-bit, missed-refresh counter is incremented.
Page 250 Consider a typical SDRAM device having two internal banks, 2K rows in each bank (4K rows total) with a refresh period of 32 ms for 2K rows. This means that the MPC8240 must refresh each internal bank (2K rows) every 32 ms. In this example there are two banks, so to refresh the whole SDRAM it takes 64 ms.
Page 251: Sdram Refresh Timing
See Chapter 14, “Power Management,” for more information on these modes. In doze and nap power saving modes, the MPC8240 supplies normal CBR refresh to SDRAM. In sleep mode, the MPC8240 can be conﬁgured to use the SDRAM self-refresh mode, provide normal refresh to SDRAM, or provide no refresh support.
Page 252: Sdram Controller Power Saving Configurations
Table 6-15. SDRAM Power Saving Modes Refresh Configuration Power Management Control Register (PMCR1) Power Saving Refresh MCCR1 Mode Type [SREN] DOZE SLEEP LP_REF_EN Doze Normal — — Normal — — — Sleep Self — — Normal — — 6-34 MPC8240 Integrated Processor User’s Manual...
Page 253: Sdram Self Refresh Entry
Figure 6-19. SDRAM Self Refresh Entry The exit timing for self-refreshing SDRAMs is shown in Figure 6-20. SDRAM CLK[0:3] SDRAS SDCAS ADDR A10 = 1 DQM[0:7] (Tri-stated) DATA 12 cycles Figure 6-20. SDRAM Self Refresh Exit Chapter 6. MPC8240 Memory Interface 6-35...
Page 254: Processor-To-Sdram Transaction Examples
Figure 6-21 and Figure 6-22 show series of processor burst and single-beat reads to SDRAM. Figure 6-23 and Figure 6-24 show series of processor burst and single-beat writes to SDRAM. Figure 6-25 shows a series of processor single-beat reads followed by writes to SDRAM. 6-36 MPC8240 Integrated Processor User’s Manual...
Page 255 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] AACK DBG0 60x Data Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Precharge Read Read Note: CAS latency = 2 Read Bank...
Page 256 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] TSIZ[0:2] AACK DBG0 60x Data Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Activate Precharge Read Read Bank A Bank B Bank A Bank B...
Page 257 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 8 60x Bus Clk ADDR ADDR ADDR ADDR 60x Address TT[0:4] AACK DBG0 60x Data Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Precharge Precharge Precharge Write Read Write...
Page 258 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 8 60x Bus Clk 60x Address ADDR ADDR ADDR ADDR TT[0:4] TSIZ[0:2] AACK DBG0 60x Data Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Precharge Precharge Read-Modify-Write Read...
Page 259 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 8 60x Bus Clk ADDR ADDR ADDR 60x Address TT[0:4] TSIZ[0:2] AACK DBG0 60x Data Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Precharge Precharge Read Read-Modify-Write Read...
Page 260: Pci-To-Sdram Transaction Examples
Figure 6-26 shows a series of PCI reads from SDRAM with Speculative Reads Enabled. Figure 6-27 shows a series of PCI reads from SDRAM with Speculative Reads Disabled. Figure 6-28 shows a series of PCI writes to SDRAM. 6-42 MPC8240 Integrated Processor User’s Manual...
Page 261 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] AACK Speculative Speculative Speculative SNOOP SNOOP SNOOP Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Bank Read Read Read...
Page 262 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR TT[0:4] AACK SNOOP SNOOP Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Bank Read Read PCI Clk FRAME A/D[31:0] ADDR ADDR...
Page 263 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] AACK SNOOP SNOOP SNOOP Memory Data SDMA[13:0] DQM[0:7] SDRAS SDCAS Activate Bank Write Write PCI Clk FRAME A/D[31:0] ADDR...
Page 264: Fpm Or Edo Dram Interface Operation
The banks can be built of DRAMs, SIMMs or DIMMs that range from 4 to 128 Mbits as described in Table 6-17. The memory design must be byte-selectable for writes using CAS. The MPC8240 allows up to 1 Gbyte of addressable memory.
Page 265: Example 16-Mbyte Dram System With Parity—64-Bit Mode
Some address and control signals may or may not require buffering, depending upon the system design. Analysis of the MPC8240 AC speciﬁcations, desired memory operating frequency, capacitive loads, and board routing loads assist the system designer in deciding whether any signals require buffering. See the MPC8240 Hardware Speciﬁcations for more information. MPC8240...
Page 266: Supported Fpm Or Edo Dram Organizations
It is not necessary to use identical memory devices in each memory bank; individual memory banks may be of differing sizes but not of different type (SDRAM). The MPC8240 can be conﬁgured to provide 9–13 row bits to a particular bank, and 7–12 column bits.
Page 267: Unsupported Multiplexed Row And Column Address Bits
2 Mbits x 8 11 x 10 4 Mbits x 4 12 x 10 4 Mbits x 4 11 x 11 16 Mbits x 1 13 x 11 1024 16 Mbits x 1 12 x 12 1024 Chapter 6. MPC8240 Memory Interface 6-49...
Page 268: Fpm Or Edo Dram Address Multiplexing
1024 6.3.2 FPM or EDO DRAM Address Multiplexing System software must conﬁgure the MPC8240 at reset to appropriately multiplex the row and column address bits for each bank. This is done by writing the row address conﬁguration into the memory control conﬁguration register 1 (MCCR1); see Section 4.10, “Memory Control Conﬁguration Registers.”...
Page 269: Column Bit Multiplexing During The Column Phase (Cas)
A[6:8, 21] A[5:8] A[unused, 7:8, 21] A[unused, 6:8] 6.3.2.3 Graphical View of the Row and Column Bit Multiplexing Figure 6-32 and Figure 6-33 provide a graphical view of the row and column bit multiplexing. Chapter 6. MPC8240 Memory Interface 6-51...
Page 270: Dram Address Multiplexing Sdma[12:0]—32 Bit Mode
8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Figure 6-32. DRAM Address Multiplexing SDMA[12:0]—32 Bit Mode 6-52 MPC8240 Integrated Processor User’s Manual...
Page 271: Dram Address Multiplexing Sdma[12:0]—64 Bit Mode
9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 6-33. DRAM Address Multiplexing SDMA[12:0]—64 Bit Mode Chapter 6. MPC8240 Memory Interface 6-53...
Page 272: Fpm Or Edo Memory Data Interface
FPM or EDO DRAM Interface Operation 6.3.3 FPM or EDO Memory Data Interface The MPC8240 supports ﬂow-through data path buffering for the DRAM data interface between the internal processor bus and external memory data bus, which must be conﬁgured as described in Table 6-19 and Table 6-20. Unspeciﬁed bit settings have undeﬁned behavior.
Page 273: Fpm Or Edo Dram Initialization
HRST_CTRL) are negated, the MEMGO bit is cleared to zero (0) which turns off the memory controller. The processor 5core starts fetching boot code from ROM (local or PCI). For systems containing FPM or EDO DRAM, the boot code must set the MPC8240 conﬁguration bit RAMTYP = 1.
Page 274: Fpm Or Edo Dram Interface Timing
MCCR2 @ <F4> After conﬁguration of all these parameters is complete, the system software must set the conﬁguration bit MEMGO which enables the memory controller. The MPC8240 performs one CAS before RAS (CBR) refresh cycle each time REFINT elapses. After eight refreshes, the main memory array is available for read and write accesses.
Page 275: Fpm Or Edo Timing Parameters
Write command setup time Write command pulse width Write to RAS hold time (CBR refresh) Write to RAS precharge time (CBR refresh) Note that all signal transitions occur on the rising edge of the memory bus clock. Chapter 6. MPC8240 Memory Interface 6-57...
Page 276: Dram Single-Beat Read Timing (No Ecc)
Figure 6-36 shows a 64-bit bus mode burst read operation. MCLK RASP RP 1 RCD 2 CAS 3 CP 4 CAS 5 CP 4 CAS 5 CP 4 CAS 5 ADDR RHCP DATA Figure 6-36. DRAM Four-Beat Burst Read Timing (No ECC)—64-Bit Mode 6-58 MPC8240 Integrated Processor User’s Manual...
Page 277: Dram Eight-Beat Burst Read Timing Configuration—32-Bit Mode
DATA Figure 6-37. DRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode Figure 6-38 shows a single-beat write operation. MCLK RP 1 RCD 2 CAS 3 ADDR DATA Figure 6-38. DRAM Single-Beat Write Timing (No ECC) Chapter 6. MPC8240 Memory Interface 6-59...
Page 278: Dram Four-Beat Burst Write Timing (No Ecc)—64-Bit Mode
MCLK RASP RP 1 CP 4 CP 4 CP 4 RCD 2 CAS 3 CAS 5 CAS 5 CAS 5 ADDR RHCP DATA Figure 6-40. DRAM Eight-beat Burst Write Timing (No ECC)—32 Bit Mode 6-60 MPC8240 Integrated Processor User’s Manual...
Page 279: Dma Burst Wrap
8-bit quantity (byte). Thus, for any write operation to system memory that is less than a double word, the MPC8240 must latch the write data, read an entire 64-bit double word from memory, check the parity of that double word, merge the write data with that double word, regenerate parity for the new double word, and ﬁnally write the new double word back to memory.
Page 280: Rmw Parity Latency Considerations
The processor core is expected to generate parity for all other memory write operations as the data goes directly to memory. Note that the MPC8240 does not support RMW parity mode when in 32-bit data path mode (RMW_PAR = 0).
Page 281: The Mpc8240 Fpm Or Edo Ecc Syndrome Encoding (Data Bits 0:31)
64-bit data path. The ECC logic in the MPC8240 detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble. Other errors may be detected but are not guaranteed to be either detected or corrected.
Page 282: Fpm Or Edo Dram Interface Timing With Ecc
FPM or EDO DRAM Interface Operation The MPC8240 supports concurrent ECC for the FPM or EDO data path and parity for the processor core data path. ECC and parity may be independently enabled or disabled. The eight signals used for ECC (PAR[0:7]) are also used for processor core parity. The MPC8240 checks ECC on all memory reads (provided ECC_EN = 1).
Page 283: Fpm Dram Burst Read With Ecc
Figure 6-42 shows an EDO burst read operation. MCLK ADDR DRAM DATA DRAM DRAM DRAM DRAM INTERNAL DATA BUS Device driving data bus MPC8240 MPC8240 MPC8240 MPC8240 Figure 6-42. EDO DRAM Burst Read Timing with ECC Chapter 6. MPC8240 Memory Interface 6-65...
Page 284: Fpm Or Edo Dram Refresh
RAS active time during a CBR refresh. (Refer to interval RAS in Figure 6-44.) As shown in the ﬁgure, the MPC8240 implements bank staggering for CBR refreshes. System software is responsible for optimal conﬁguration of interval RAS after system start-up.
Page 285: Fpm Or Edo Dram Power Saving Modes
The MPC8240’s memory interface provides for sleep, doze, and nap power saving modes deﬁned for the processor core. In doze and nap modes, the MPC8240 supplies normal CBR refresh to DRAM. In sleep mode, the MPC8240 can be conﬁgured to take advantage of DRAM self-refresh mode, to provide normal refresh to DRAM, or to provide no refresh support.
Page 286: Dram Self-Refresh In Sleep Mode
— 6.3.11.2 DRAM Self-Refresh in Sleep Mode The MPC8240 allows the system designer to use DRAMs that provide self refresh for power-down situations. These DRAMs should be used if data retention is imperative during sleep mode. The MPC8240 properly conﬁgures these DRAMs during sleep mode if the appropriate conﬁguration register bit is set.
Page 287: Pci-To-Dram Transaction Examples
Figure 6-46 shows a series of PCI reads from DRAM with Speculative Reads Enabled. Figure 6-47 shows a series of PCI reads from DRAM with Speculative Reads Disabled. Figure 6-48 shows a series of PCI writes to DRAM. Chapter 6. MPC8240 Memory Interface 6-69...
Page 288 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] AACK Speculative Speculative Speculative SNOOP SNOOP SNOOP D0/D1 D2/D3 D4/D5 D6/D7 D8/D9 DA/DB DC/DD DE/DF D0/D1 D2/D3 D4/D5...
Page 289 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR TT[0:4] AACK SNOOP SNOOP Mem Data D0/D1 D2/D3 D4/D5 D6/D7 D8/D9 DA/DB DC/DD DE/DF Mem Address RASn CASn Sys Clk FRAME...
Page 290 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 60x Bus Clk 60x Address ADDR ADDR ADDR TT[0:4] AACK SNOOP SNOOP SNOOP Mem Data D0/D1 D2/D3 D4/D5 D6/D7 D8/D9 DA/DB Mem Address ROW COL RASn CASn Sys Clk...
Page 291: Rom/Flash Interface Operation
ROM/Flash Interface Operation 6.4 ROM/Flash Interface Operation For the ROM/Flash interface, the MPC8240 provides 21 address bits, two chip selects, one Flash output enable (FOE), and one ﬂash write enable (WE). Figure 6-49 displays a block diagram of the ROM interface.
Page 292: Mbyte Rom System Including Parity Paths To Dram—64-Bit Mode
RCS0 is connected to all CE in Bank 0 (8 Mbytes) and RCS1 is connected to all CE in Bank 1 (8 Mbytes). Figure 6-50. 16-Mbyte ROM System Including Parity Paths to DRAM—64-Bit Mode 6-74 MPC8240 Integrated Processor User’s Manual...
Page 293 Figure 6-51. 2-Mbyte Flash Memory System Including Parity Paths to DRAM—8-Bit Mode The MPC8240 supports an 8-, 32-, or 64-bit data path to bank 0. A conﬁguration signal (FOE) sampled at reset, determines the bus width of the ROM or Flash device (8-bit, 32-bit, or 64-bit) in bank 0.
Page 294: Reset Configurations Of Rom/Flash Controller
For systems using the 8-bit interface to bank 0, the ROM/Flash device must be connected to the most-signiﬁcant byte lane of the data bus MDH[0:7]. The MPC8240 performs byte- lane alignment for single-byte reads from ROM/Flash memory. The MPC8240 can also perform byte gathering for up to 8 bytes for ROM/Flash read operations.
Page 295: Rom/Flash Address Multiplexing
PCI bus. The RCS0 signal is sampled at reset to determine the location of ROM/Flash. If the system ROM space is mapped to the PCI bus, the MPC8240 directs all system ROM accesses to the PCI bus.
Page 296: Or 32-Bit Rom/Flash Interface Timing
Figure 6-54. ROM/Flash Address Multiplexing—64-Bit Mode 6.4.2 64 or 32-Bit ROM/Flash Interface Timing The MPC8240 provides 20 address bits with which to access 8 Mbytes of external 64-bit ROM and 21 address bits with which to access 8 Mbytes of external 32-bit ROM. In addition, two ROM chip selects (RCS0, RCS1) allow addressing of ROM memories of up to 16 Mbytes.
Page 297 The MPC8240’s two ROM chip select outputs are decoded from the memory address and can be used as bank selects. The MPC8240 can access 16 Mbytes of ROM in systems that have a 64-bit memory bus (8 Mbytes each in bank RSC0 and bank RSC1). In this mode, bank select RCS0 decodes addresses 0xFF80_0000–FFFF_FFFF, and RCS1 decodes...
Page 298 Data sampled ROMFAL (ROM first access latency) = 3–34 clocks ROMNAL (ROM nibble access latency) = 0–9 clocks MCCR1[BURST] = 1 Figure 6-56. Read Access Timing (Cache Block) for Burst ROM/Flash Devices in 64-Bit Mode 6-80 MPC8240 Integrated Processor User’s Manual...
Page 299: Bit Rom/Flash Interface Timing
The MPC8240 provides 21 address bits for accessing 2 Mbytes of external 8-bit ROM/Flash memory. The most signiﬁcant address bit is SDMA12/SDBA1. The next eight most signiﬁcant address bits are provided as an alternate function on the MPC8240’s parity signals, PAR[0:7] (AR[19:12]). The remaining 12 low-order address bits are provided on the MPC8240’s SDBA[0] (AR[11]) and SDMA[10:0] (AR[10:0]) signals with SDMA[0]...
Page 300: Bit Rom/Flash Interface—Single-Byte Read Timing
Data sampled Figure 6-58. 8-Bit ROM/Flash Interface—Single-Byte Read Timing Two-byte reads MCLK A[0:19] RCSn DATA DATA DATA 2 cycles ROMFAL 2 cycles ROMFAL (constant) (constant) Data sampled Figure 6-59. 8-Bit ROM/Flash Interface—Two-Byte Read Timing 6-82 MPC8240 Integrated Processor User’s Manual...
Page 301: Rom/Flash Interface Write Operations
The MPC8240 accommodates only single-beat writes to Flash memory. If an attempt is made to write to Flash with a data size other than the full data path size, the MPC8240 does not report an error. Thus, if software is writing to Flash, the write operations should be sized to the data path width (8, 32 or 64 bits) since there is only a single write enable (WE) strobe available.
Page 302: Rom/Flash Interface Write Timing
The ﬁgures in this section provide examples of signal timing for PCI-to-ROM/Port X transactions. Figure 6-62 shows a series of PCI reads from ROM/Port X(64-Bit). Figure 6-63 shows a series of PCI reads from ROM/Port X (8-Bit). 6-84 MPC8240 Integrated Processor User’s Manual...
Page 303 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 Mem Bus Clk Mem Data AR[19:0] RCS0 RCS1 PCI Clk FRAME A/D[31:0] ADDR ADDR C/BE[3:0] IRDY TRDY STOP Target Disconnect...
Page 304 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 Mem Bus Clk Mem Data AR[19:0] RCS0 RCS1 PCI Clk FRAME A/D[31:0] ADDR C/BE[3:0] IRDY TRDY STOP Target Retry...
Page 305 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 Mem Bus Clk Mem Data AR[19:0] RCS0 RCS1 PCI Clk FRAME A/D[31:0] ADDR ADDR C/BE[3:0] IRDY TRDY STOP Target Target Retry Disconnect...
Page 306 12345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 9012345 7 6 Mem Bus Clk Mem Data AR[19:0] RCS0 RCS1 PCI Clk FRAME A/D[31:0] ADDR ADDR C/BE[3:0] IRDY TRDY STOP Target Disconnect...
Page 307: Port X Interface
ROM/Flash interface capabilities with general purpose I/O devices it is possible to conﬁgure a wide range of devices with the MPC8240. Note that the Port X interface shares the MPC8240 ROM/Flash state machine and so the timing conﬁgurations used for ROM/Flash also apply to Port X (that is, a system cannot set up different timings for ROM/Flash and Port X).
Page 308: Port X Peripheral Interface Block Diagram
Write output enable Figure 6-64. Port X Peripheral Interface Block Diagram Because the MPC8240 shares the Port X interface with the Flash interface, only single-beat writes to Port X are supported. Therefore, care must be taken if the Port X memory space is marked as cacheable (as burst writes for cache block castouts are not supported).
Page 309: Example Of Port X Peripheral Connected To The Mpc8240
Address path SDRAM or DRAM Array Address path Flash or ROM SDMA[12:0] BUFFERS ROM Chip Select 0 to ROM RCS0 D[0:63] A0:A18 Port X I/O Device (s) RCS1 Figure 6-65. Example of Port X Peripheral Connected to the MPC8240 Chapter 6. MPC8240 Memory Interface 6-91...
Page 310: Example Of Port X Peripheral Connected To The Mpc8240
Address path SDRAM or DRAM Array Address path Flash or ROM SDMA[12:0] BUFFERS D[0:7] Reg select[0:1] Port X I/O Device (s) RCS1 Figure 6-66. Example of Port X Peripheral Connected to the MPC8240 MCLK A[0:19] ASFALL ASRISE RCS[0:1] DATA DATA 2 cycles...
Page 311: Port X Example Write Access Timing
ROM/Flash Interface Operation MCLK A[0:19] ASFALL ASRISE RCS[0:1] DATA DATA 2 cycles ROMFAL (constant) Figure 6-68. Port X Example Write Access Timing Chapter 6. MPC8240 Memory Interface 6-93...
Page 312 ROM/Flash Interface Operation 6-94 MPC8240 Integrated Processor User’s Manual...
Page 313: Pci Interface Overview
MPC8240 to handle two separate PCI transactions simultaneously. For example, if the MPC8240, as an initiator, is trying to run a burst-write to a PCI device, it may get disconnected before ﬁnishing the transaction. If another PCI device is granted the PCI bus and requests a burst-read from local memory, the MPC8240, as a target, can accept the burst-read transfer.
Page 314: Address Maps
PCI-accessible conﬁguration registers. The MPC8240 can function as either a PCI host bridge referred to as ‘host mode’ or a peripheral device on the PCI bus referred to as ‘agent mode’. Note that agent mode is supported only for address map B.
Page 315: The Mpc8240 As A Pci Target
PCI Interface Overview 7.1.2 The MPC8240 as a PCI Target As a target, upon detection of a PCI address phase the MPC8240 decodes the address and bus command to determine if the transaction is for local memory. If the transaction is destined for local memory, the target interface latches the address, decodes the PCI bus command, and forwards them to an internal control unit.
Page 316: Pci Bus Arbitration
PCI bus cycles are consumed due to arbitration (except when the bus is idle). The MPC8240 provides bus arbitration logic for the MPC8240 and up to ﬁve other PCI bus masters. The on-chip PCI arbiter is independent of host or agent mode. The on-chip PCI arbiter functions in both host and agent modes, or it can be disabled to allow for an external PCI arbiter.
Page 317: Processor-Initiated Transactions To Pci Bus
PCI bus or by the PCI latency timer described in Section 4.2.6, “Latency Timer—Offset 0x0D.” However, this case does not constitute a PCI transaction boundary, and when the MPC8240 regains mastership of the external PCI bus, the processor transaction in progress continues without rearbitration with the DMA controller.
Page 318: Pci Bus Arbiter Operation
The on-chip PCI arbiter uses a programmable two-level, round-robin arbitration algorithm. Each of the ﬁve external masters, plus the MPC8240, can be programmed for two priority levels, high or low, using the appropriate bits in the PACR. Within each priority group (high or low), the PCI bus grant is asserted to the next requesting device in numerical order, with the MPC8240 positioned before device 0.
Page 319: Pci Bus Parking
In Figure 7-2, the grant sequence (with all devices except device 4 requesting the bus and device 3 being the current master) is 0, 2, MPC8240, 0, 2, 1, 0, 2, 3, … and repeating. If device 2 is not requesting the bus, then the grant sequence is 0, MPC8240, 0, 1, 0, 3, … and repeating.
Page 320: Power-Saving Modes And The Pci Arbiter
PCI devices to run transactions. 7.2.5 Broken Master Lock-Out The PCI bus arbiter on the MPC8240 has a feature that allows it to lock out any masters that are broken or ill-behaved. The broken master feature is controlled by programming bit 12 of the PCI arbitration control register (0b0 = enabled, 0b1 = disabled).
Page 321: Basic Transfer Control
A PCI bus command is encoded in the C/BE[3:0] signals during the address phase of a PCI transaction. The bus command indicates to the target the type of transaction the initiator is requesting. Table 7-2 describes the PCI bus commands as implemented by the MPC8240. Chapter 7. PCI Bus Interface...
Page 322: Pci Bus Commands
PCI memory space, depending on the address. When a PCI master issues a memory-read command to local memory, the MPC8240 (the target) fetches data from the requested address to the end of the cache line (32 bytes) from local memory, even though all of the data may not be requested by (or sent to) the initiator.
Page 323: Addressing
Access to the PCI memory and I/O space is straightforward, although one must take into account the MPC8240 address map (map A or map B) being used. The address maps are described in Chapter 3, “Address Maps.” Access to the PCI conﬁguration space is described in Section 7.4.5, “Conﬁguration Cycles.”...
Page 324: Memory Space Addressing
As an initiator, the MPC8240 always encodes AD[1:0] = 0b00 for PCI memory space accesses. As a target, the MPC8240 executes a target disconnect after the ﬁrst data phase completes if AD[1:0] = 0b01 or AD[1:0] = 0b11 during the address phase of a local memory access.
Page 325: Device Selection
DEVSEL one clock cycle following the address phase. As an initiator, if the MPC8240 does not detect the assertion of DEVSEL within four clock cycles after the address phase (that is, ﬁve clock cycles after it asserts FRAME), it terminates the transaction with a master-abort termination;...
Page 326: Bus Driving And Turnaround
PCI Bus Transactions If the MPC8240, as a target, detects no byte enables asserted, it completes the current data phase with no permanent change. This implies that on a read transaction the MPC8240 expects that the data is not changed, and on a write transaction, that ‘the data is not stored.
Page 327: Pci Single-Beat Read Transaction
PCI Bus Transactions AD[31:0] as data signals. The turnaround cycle is enforced by the target with the TRDY signal. The target provides valid data at the earliest one cycle after the turnaround cycle. The target must drive the AD[31:0] signals when DEVSEL is asserted. During the data phase, the C/BE[3:0] signals indicate which byte lanes are involved in the current data phase.
Page 328: Pci Write Transactions
(IRDY negated). Figure 7-5 illustrates a PCI single-beat write transaction. Figure 7-6 illustrates a PCI burst write transaction. PCI_SYNC_IN AD[0:31] ADDR DATA C/BE[0:3] Byte enables FRAME IRDY DEVSEL TRDY Figure 7-5. PCI Single-Beat Write Transaction 7-16 MPC8240 Integrated Processor User’s Manual...
Page 329: Transaction Termination
PCI Bus Transactions PCI_SYNC_IN AD[0:31] ADDR DATA1 DATA2 DATA3 DATA4 C/BE[0:3] Byte enables 1 Byte enables 2 Byte enables 3 BEs 4 FRAME IRDY DEVSEL TRDY Figure 7-6. PCI Burst Write Transaction 7.4.3 Transaction Termination A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately responsible for concluding all transactions, regardless of the cause of the termination.
Page 330: Target-Initiated Termination
PCI Bus Transactions As an initiator, if the MPC8240 does not detect the assertion of DEVSEL within four clock cycles following the address phase (ﬁve clock cycles after asserting FRAME), it terminates the transaction with a master-abort. On reads that are master-aborted, the MPC8240 returns all 1s (0xFFFF).
Page 331 • The 16-clock latency timer has expired, and the ﬁrst data phase has not begun. As a target, the MPC8240 responds with a target-abort if a PCI master attempts to write to the ROM/Flash ROM space in address map B. For PCI writes to local memory, if an address parity error or data parity error occurs, the MPC8240 aborts the transaction internally but continues the transaction on the PCI bus.
Page 332: Pci Target-Initiated Terminations
STOP Disconnect A Disconnect B PCI_SYNC_IN FRAME IRDY DEVSEL TRDY STOP Retry PCI_SYNC_IN PCI_SYNC_IN FRAME FRAME IRDY IRDY DEVSEL DEVSEL TRDY TRDY STOP STOP Disconnect without data Target abort Figure 7-7. PCI Target-Initiated Terminations 7-20 MPC8240 Integrated Processor User’s Manual...
Page 333: Fast Back-To-Back Transactions
As an initiator, the MPC8240 does not perform any fast back-to-back transactions. As a target, the MPC8240 supports both types of fast back-to-back transactions.
Page 334: Standard Pci Configuration Header
Cache line size Speciﬁes the system cache line size in 32-bit units 0x0D Latency timer Speciﬁes the value of the latency timer in PCI bus clock units for the device when acting as an initiator 7-22 MPC8240 Integrated Processor User’s Manual...
Page 335 CONFIG_ADDR is set and the device number is not 0b1_1111). For the MPC8240, the CONFIG_ADDR register is located at different addresses depending on the memory address map in use. The address maps are described in Chapter 3, “Address Maps.”...
Page 336: Config_Addr Register Format
23–16 Bus number This ﬁeld is an encoded value used to select the target bus of the conﬁguration access. For target devices on the PCI bus connected to the MPC8240, this ﬁeld should be set to 0x00. 15–11 Device number This ﬁeld is used to select a speciﬁc device on the target bus.
Page 337: Type 0 Configuration Translation
See Section 7.4.6, “Other Bus Transactions,” for more information. If the bus number corresponds to the local PCI bus (bus number = 0x00), the MPC8240 performs a type 0 conﬁguration cycle translation. If the bus number indicates a remote PCI bus (that is, nonlocal), the MPC8240 performs a type 1 conﬁguration cycle translation.
Page 338: Type 0 Configuration—Device Number To Idsel Translation
A device number of all 1s indicates a PCI special-cycle or interrupt-acknowledge transaction. Note that the MPC8240 must not issue PCI conﬁguration transactions to itself (that is, for PCI conﬁguration transactions initiated by the MPC8240, its IDSEL input signal must not be asserted).
Page 339: Other Bus Transactions
(EPIC) Unit,” for more information about the EPIC unit. When the MPC8240 detects a read to the CONFIG_DATA register, it checks the enable ﬂag and the device number in the CONFIG_ADDR register. If the enable bit is set, the bus...
Page 340: Special-Cycle Transactions
(0b00_0000), then the MPC8240 performs a special-cycle transaction on the local PCI bus. If the bus number indicates a nonlocal PCI bus, the MPC8240 performs a type 1 conﬁguration cycle translation, similar to any other conﬁguration cycle for which the bus number does not match.
Page 341: Exclusive Access
Exclusive Access initiator of the special-cycle transaction can insert wait states but since there is no speciﬁc target, the special-cycle message and optional data ﬁeld are valid on the ﬁrst clock IRDY is asserted. All special-cycle transactions are terminated by master-abort; however, the master-abort bit in the initiator’s status register is not set for special-cycle terminations.
Page 342: Completing An Exclusive Access
If a locked operation covers more than one cache line (32 bytes), only the most recently accessed cache line is locked from the processor. Since a snoop transaction is required to establish a lock, the MPC8240 does not honor the assertion of LOCK when PICR1[NO_SNOOP_EN] is set.
Page 343: Pci Parity
PCI Error Functions 7.6.1 PCI Parity Generating parity is not optional; it must be performed by all PCI-compliant devices. All PCI transactions, regardless of type, calculate even parity; that is, the number of 1s on the AD[31:0], C/BE[3:0], and PAR signals all sum to an even number. Parity provides a way to determine, on each transaction, if the initiator successfully addressed the target and transferred valid data.
Page 344: Error Reporting
Section 2.4, “Conﬁguration Signals Sampled at Reset.” Note that agent mode is supported only for address map B. It is a conﬁguration error to set the MPC8240 to use address map A and agent mode. Also note that in agent mode, the MPC8240 ignores all PCI memory accesses (except to the EUMB) until inbound address translation is enabled.
Page 345: Initialization Options For Pci Controller
7.7.2 Accessing the MPC8240 Conﬁguration Space The MPC8240 responds to PCI conﬁguration accesses from external PCI agents when the MPC8240’s IDSEL input signal is asserted. This allows an external agent access to a subset of the MPC8240’s internal conﬁguration registers. The conﬁguration of the internal registers of the MPC8240 that are not accessible to external agents is described in Section 4.1, “Conﬁguration Register Access.”...
Page 346: Pci Address Translation Support
PCI memory space. Note that address translation is supported only for agent mode; it is not supported when the MPC8240 is operating in host mode. Also note that since agent mode is supported only for address map B, address translation is supported only for address map B.
Page 347: Initialization Code Translation In Agent Mode
4. The system host controller initializes and conﬁgures the MPC8240 as an agent. 5. The host must program PCSRBAR to locate the EUMB within PCI memory space. 6. The host must set bit 1 of the PCI command register to enable MPC8240 response to PCI memory accesses.
Page 348 PCI Host and Agent Modes 7-36 MPC8240 Integrated Processor User’s Manual...
Page 349: Dma Overview
PCI hosts. Data movement occurs on the PCI and/or memory bus. The MPC8240 has two DMA channels, each with a 64-byte queue to facilitate the gathering and sending of data. Both the local processor and PCI masters can initiate a DMA transfer.
Page 350: Dma Register Summary
Figure 8-1. DMA Controller Block Diagram 8.2 DMA Register Summary There are two complete sets of DMA registers on the MPC8240—one for channel 0 and one for channel 1. The DMA registers of the MPC8240 comprise part of the MPC8240 embedded utilities and are memory mapped.
Page 351: Dma Operation
DMA Operation Table 8-1. DMA Register Summary Local PCI Memory Memory Register Name Description Offset Offset 0x100 0x0_1100 DMA 0 mode register Allows software to setup up different DMA modes (DMR) and interrupt enables 0x104 0x0_1104 DMA 0 status register Tracks DMA processes and errors (DSR) 0x108...
Page 352: Dma Direct Mode
PCI cache line size register is set to 0x08 (32-byte cache size). Otherwise, write operations are performed. The internal DMA protocols operate on a cache line basis, so the MPC8240 always attempts to perform transfers that are the size of a cache line. The only possible exceptions are the ﬁrst or last transfer.
Page 353: Dma Chaining Mode
DMA chaining mode can be used to implement scatter gathering. In scatter gathering with the MPC8240, a group of descriptors can transfer (scatter) data from a contiguous space of memory to a non-contiguous destination or, likewise, data from a non-contiguous destination can be gathered to a contiguous region of memory.
Page 354: Periodic Dma Feature
This feature has potential use in applications that require periodic movement of data. The MPC8240 uses two of the timers in the EPIC unit to automatically signal the DMA channels to start a DMA process, without the use of the processor interrupt.
Page 355: Dma Operation Flow
DMA Operation 8.3.3 DMA Operation Flow Figure 8-2 shows a general ﬂow diagram for the operation of the DMA controller on the MPC8240. Periodic mode Chaining mode Direct mode Save CDAR Load the parameters from memory into the DMA registers Timer Expires.
Page 356: Dma Coherency
Section 8.7.3, “Current Descriptor Address Registers (CDARs),” and Section 8.7.8, “Next Descriptor Address Registers (NDARs),” respectively. The MPC8240 architecture assumes that all of the local or host memory is prefetchable including Port X. Note that this results in multiple reads occurring to the same location on the memory interface and Port X.
Page 357: Dma Transfer Types
DMA Transfer Types Another factor that can affect DMA performance is access to the PCI bus. For more information on the DMA arbitration boundaries for the PCI bus, see Section 7.2.1, “Internal Arbitration for PCI Bus Access.” 8.4 DMA Transfer Types The DMA controller supports four types of transfer—PCI to PCI;...
Page 358: Address Map Interactions
8.5.2.1 PCI Master Abort when PCI Bus Speciﬁed for Lower 2-Gbyte Space If the MPC8240 is in host mode and a transferred address falls within the lower 2-Gbyte space (0x0000_0000 to 0x7FFF_FFFF) on the PCI bus (speciﬁed by CDAR[CTT]), then the MPC8240 issues the transaction to the PCI bus with that address.
Page 359: Attempted Reads From Rom On The Pci Bus—Host Mode
If the MPC8240 is in host mode, CDAR[CTT] indicates that the transferred address is for local ROM space and the MPC8240 is conﬁgured for ROM on the PCI bus, then the transaction is performed to the local ROM interface. Unknown data will be returned. (This is considered a programming error.)
Page 360: Attempted Access To Rom On The Pci Bus—Agent Mode
EOTD bit in this descriptor ﬁeld must be set. Byte count Contains the number of bytes to transfer. When the DMA controller reads the descriptor from memory, this ﬁeld is loaded into the BCR as described in Table 8-8. 8-12 MPC8240 Integrated Processor User’s Manual...
Page 361: Chaining Of Dma Descriptors In Memory
DMA Descriptors for Chaining Mode Figure 8-3 shows how the DMA descriptors in memory are chained together. Current Descriptor Address Register Local Memory or PCI Memory Offset Source address 0x00 Reserved 0x04 Descriptor 0 0x08 Destination address 0x0C Reserved Next descriptor 0x10 Reserved 0x14...
Page 362: Descriptors In Big-Endian Mode
Results: Source Address = 0x44332211 <MSB..LSB> Destination Address = 0x88776655 <MSB..LSB> Next Descriptor Address = 0x12345678 <MSB..LSB> Byte Count = 0x76543210 <MSB..LSB> Note that the descriptor struct must be aligned on an 8-word (32-byte) boundary. 8-14 MPC8240 Integrated Processor User’s Manual...
Page 363: Dma Register Descriptions
DMA Register Descriptions 8.7 DMA Register Descriptions The following sections describe the DMA controller registers and their bit settings in detail. Note that the PCI address offset is listed as part of the register descriptions table titles. For the local memory offsets, see Table 8-1. 8.7.1 DMA Mode Registers (DMRs) The DMRs allow software to start the DMA transfer and to control various DMA transfer characteristics.
Page 364: Dmr Field Descriptions—Offsets 0X100, 0X200
Allows the DMA controller to hold the source address to a ﬁxed value for every transfer. The size used for the transfers is indicated by SAHTS. The MPC8240 only supports aligned transfers for this feature. Only one of DAHE or SAHE may be set at one time.
Page 365 Channel continue. This bit applies only to chaining mode and is cleared by the MPC8240 after every descriptor read. It is typically set after software dynamically adds more descriptors to a chain that is currently in progress or to a ﬁnished chain.
Page 366: Dma Status Registers (Dsrs)
DMR and CDAR. Figure 8-5 shows the bits in the DSRs. Reserved EOCAI EOSI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-5. DMA Status Register (DSR) 8-18 MPC8240 Integrated Processor User’s Manual...
Page 367: Current Descriptor Address Registers (Cdars)
— Reserved Channel busy 0 Channel not busy. This bit is cleared by the MPC8240 as a result of an error or when the DMA transfer is ﬁnished. 1 A DMA transfer is currently in progress. EOSI End-of-segment interrupt Write1 clears 0 No end-of-segment condition.
Page 368: Source Address Registers (Sars)
In agent mode, all DMA to PCI read transactions are translated if the SAR address is within the outbound translation window. See Section 3.3.2, “Outbound PCI Address Translation,” for more information. 8-20 MPC8240 Integrated Processor User’s Manual...
Page 369: Destination Address Registers (Dars)
All 0s Destination address. This register contains the destination address of the DMA transfer. The content is updated by the MPC8240 after every DMA write operation. 8.7.6 Byte Count Registers (BCRs) The BCRs contain the number of bytes per transfer. The maximum transfer size is 64 Mbytes - 1 byte.
Page 370: Dar And Bcr Values—Double Pci Write
25–0 All 0s Byte count. Contains the number of bytes to transfer. The value in this register is automatically decremented by the MPC8240 after each DMA read operation until BCR = 0. 8.7.7 DAR and BCR Values—Double PCI Write Note that when the DMA controller is programmed for local memory to PCI or PCI-to-PCI memory transfers, certain values programmed in the DAR and BCR can cause the DMA controller to write the last beat of data twice.
Page 371: Next Descriptor Address Registers (Ndars)
DMA Register Descriptions 8.7.8 Next Descriptor Address Registers (NDARs) The NDARs contain the address for the next descriptor in memory. Software is not expected to initialize this register. This register contains valid information only after the DMA engine has fetched a descriptor that was pointed to by the CDAR. All data bits, with the exception of EOTD, belong to the next descriptor to be loaded and executed.
Page 372 DMA Register Descriptions 8-24 MPC8240 Integrated Processor User’s Manual...
Page 373: Message Unit (Mu) Overview
Because of the independent nature of the tasks, it is necessary to provide a communication mechanism between the peripheral processors and the rest of the system. The MU of the MPC8240 provides the following features which can be used for this communication: •...
Page 374: Message And Doorbell Register Programming Model
The message and doorbell registers can also be used to perform peer-to-peer communication such as between multiple MPC8240 devices in a system. In this scenario, only the inbound registers need to be used and should be all mapped to different PCSRBAR locations.
Page 375: Message Register Descriptions
Message and Doorbell Register Programming Model 9.2.2 Message Register Descriptions The IMRs allow a remote host or PCI master to write a 32-bit value that automatically generates an interrupt to the processor core through the EPIC unit. The OMRs allow the processor core to write an outbound message that automatically causes the outbound interrupt signal INTA to be asserted on the PCI bus.
Page 376: Outbound Doorbell Register (Odbr)
1 from external interrupt (INTA) to be signalled if IMIMR[ODIM] = 0; PCI clears the bit. it also causes OMISR[ODI] to be set MPC8240 Integrated Processor User’s Manual...
Page 377: Pci Configuration Identification
The IOP dedicates a certain space in its local memory to hold inbound (from the remote processor) and outbound (to the remote processor) messages. The space is managed as memory-mapped FIFOs with pointers to this memory maintained through the MPC8240 I O registers. 9.3.1 PCI Conﬁguration Identiﬁcation The I O speciﬁcation deﬁnes extensions for the PCI bus through which message queues are...
Page 378: I 2 O Register Summary
One FIFO in each queue tracks the free MFAs (free_list FIFO). The other FIFO tracks the MFAs that have posted messages (post_list FIFO). These FIFOs are managed by the remote processors and the processor core through the MPC8240 I registers. For more information, see Section 9.3.2, “I2O Register Summary”.
Page 379: Inbound Fifos
O Interface Figure 9-4 shows an example of the message queues: Inbound Free List Message FIFO Frame Head Pointer Processor Message Frame Core Write PCI Master Message Read Tail Pointer Frame Inbound Message Queue Frame Inbound Head Port Post List Message Pointer PCI Master...
Page 380: Inbound Free_List Fifo
The inbound post_list FIFO holds MFAs that are posted to the processor core from external PCI masters. PCI masters external to the MPC8240 write to the head of the FIFO by writing the MFA to the inbound FIFO queue port register (IFQPR). The I O unit transfers the MFA to the location pointed to by the inbound post_FIFO head pointer register (IPHPR).
Page 381: Outbound Post_List Fifo
O, doorbell register, and outbound message register events that cause the assertion of INTA. These events are generated by blocks in the MPC8240 and the assertion of INTA signals an interrupt to the PCI bus on behalf of these blocks.
Page 382: Outbound Message Interrupt Mask Register (Omimr)
OMR0). Set independently of the mask bit in OMIMR. 9.3.4.1.2 Outbound Message Interrupt Mask Register (OMIMR) The OMIMR contains the interrupt masks of the I O, doorbell register, and message register events generated by the MPC8240. 9-10 MPC8240 Integrated Processor User’s Manual...
Page 383: Inbound Fifo Queue Port Register (Ifqpr)
O Interface Figure 9-6 shows the bits of the OMIMR. Reserved OM0IM OM1IM ODIM OPQIM 0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 Figure 9-6. Outbound Message Interrupt Mask Register (OMIMR) Table 9-10 shows the bit settings for the OMIMR.
Page 384: Outbound Fifo Queue Port Register (Ofqpr)
IMISR (DMC and IDI) are cleared by writing a 0b1 to the corresponding machine check and interrupt bits in IDBR (causing them to be cleared). 9-12 MPC8240 Integrated Processor User’s Manual...
Page 385: Inbound Message Interrupt Status Register (Imisr)
O Interface Figure 9-9 shows the bits of the IMISR. Reserved IM0I IM1I IPQI IPOI OFOI 0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 Figure 9-9. Inbound Message Interrupt Status Register (IMISR) Table 9-13 shows the bit settings for the IMISR.
Page 386: Inbound Message Interrupt Mask Register (Imimr)
Reserved IM0IM IM1IM IDIM MCIM IPQIM IPOIM OFOIM 0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 Figure 9-10. Inbound Message Interrupt Mask Register (IMIMR) 9-14 MPC8240 Integrated Processor User’s Manual...
Page 387: Inbound Free_Fifo Head Pointer Register (Ifhpr)
O Interface Table 9-14 shows the bit settings for the IMIMR. Table 9-14. IMIMR Field Descriptions—Offset 0x0_0104 Reset Bits Name Description Value 31–9 — All 0s Reserved OFOM Outbound free_list overﬂow mask 0 Outbound free_list overﬂow is allowed (and causes assertion of mcp). 1 Outbound free_list overﬂow is masked.
Page 388: Inbound Free_Fifo Tail Pointer Register (Iftpr)
PCI masters post MFAs to the inbound post_list FIFO pointed to by the inbound post_FIFO head pointer register (IPHPR). The actual PCI writes are performed through the inbound FIFO queue port register (IFQPR). The MPC8240 automatically increments the IPHP value after every write to IFQPR. Figure 9-13 shows the bits of the IPHPR.
Page 389: Inbound Post_Fifo Tail Pointer Register (Iptpr)
O Interface Reserved IPHP 20 19 Figure 9-13. Inbound Post_FIFO Head Pointer Register (IPHPR) Table 9-17 shows the bit settings for the IPHPR. Table 9-17. IPHPR Field Descriptions—Offset 0x0_0130 Reset Bits Name Description Value 31–20 All 0s Queue base address. When read, this ﬁeld returns the contents of QBAR[31–20]. 19–2 IPHP All 0s...
Page 390: Outbound Free_Fifo Head Pointer Register (Ofhpr)
(IFHPR). The actual PCI writes of MFAs are performed through the outbound FIFO queue port register (OFQPR). The MPC8240 automatically increments the OFTP value after every read from OFQPR. Figure 9-15 shows the bits of the OFHPR.
Page 391: Outbound Post_Fifo Head Pointer Register (Ophpr)
PCI masters pick up posted MFAs from the outbound post_list FIFO pointed to by the outbound post_FIFO tail pointer register (OPTPR). The actual PCI reads of MFAs are performed through the outbound FIFO queue port register (OFQPR). The MPC8240 automatically increments the OPTP value after every read from OFQPR.
Page 392: Messaging Unit Control Register (Mucr)
0 PCI writes to IFQPR and OFQPR are ignored and reads return 0xFFFF_FFFF. 1 Allows PCI masters to access the inbound and outbound queue ports (IFQPR and OFQPR). Usually, this bit is set only after software has initialized all pointers and conﬁguration registers. 9-20 MPC8240 Integrated Processor User’s Manual...
Page 393: Queue Base Address Register (Qbar)
O Interface 9.3.4.2.12 Queue Base Address Register (QBAR) The QBAR speciﬁes the beginning address of the circular queue structure in local memory. Figure 9-20 shows the bits of the QBAR. Reserved 0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0 20 19 Figure 9-20.
Page 394 O Interface 9-22 MPC8240 Integrated Processor User’s Manual...
Page 395 This feature allows for complex applications with multiprocessor control. 10.1.1 I C Unit Features The I C unit on the MPC8240 consists of a transmitter/receiver unit, a clocking unit, and a control unit. Some of the features of the I C unit are as follows: • Two-wire interface •...
Page 396 SCL (serial clock) HIGH When the MPC8240 is idle or acts as a slave, SCL defaults as an input. The unit uses SCL to synchronize incoming data on SDA. The bus is assumed to be busy when SCL is detected low.
Page 397 C Protocol 10.1.4 I C Block Diagram The reset state of the I C interface is as a slave receiver. Thus, when not explicitly programmed to be a master or to respond to a slave transmitter address, the I C unit always defaults to slave receiver operation.
Page 398: Start Condition
C device cannot be master and slave at the same time. The MPC8240 does not respond to a general call (broadcast) command unless the calling address matches its slave address. Because general call broadcasts an address of 0b0000_000, only MPC8240s with a slave address of 0b0000_000 would respond. When this occurs, the MPC8240 drives SDA low during the address acknowledge cycle.
Page 399: Data Transfer
If two or more masters try to control the bus simultaneously, each master (including the MPC8240) has a clock synchronization procedure that determines the bus clock—the low period is equal to the longest clock low period, and the high is equal to the Chapter 10.
Page 400: Clock Synchronization
Note that the MPC8240 does not automatically retry a failed transfer attempt. If the I C module of the MPC8240 is enabled in the middle of an ongoing byte transfer, the interface behaves as follows: • Slave mode—the MPC8240 ignores the current transfer on the bus and starts operating whenever a subsequent START condition is detected.
Page 401: Handshaking
C interface responds to when addressed as a slave. Note that it is not the address sent on the bus during the address calling cycle when the MPC8240 is in master mode. Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR Figure 10-3.
Page 402: I2Cadr Field Descriptions—Offset 0X0_3000
Reserved 7–1 ADDR 0x00 Slave address. Contains the speciﬁc address to which the MPC8240 responds as a slave on the I C interface. Note that the default mode of the C interface is slave mode for an address match. —...
Page 403: Serial Bit Clock Frequency Divider Selections
C Register Descriptions Table 10-5 maps the I2CFDR[FDR] ﬁeld to the clock divider values. Table 10-5. Serial Bit Clock Frequency Divider Selections Divider Divider (Decimal) (Decimal) 0x00 0x20 0x01 0x21 0x02 0x22 0x03 0x23 0x04 0x24 0x05 0x25 0x06 0x26 0x07 0x27 0x08...
Page 404: I2Ccr Field Descriptions—Offset 0X0_3008
I2CSR[SRW]. In master mode, the bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive mode 1 Transmit mode The MTX bit is cleared when the master loses arbitration. 10-10 MPC8240 Integrated Processor User’s Manual...
Page 405 I C module is conﬁgured as a receiver, not a transmitter and does not apply to address cycles; when the MPC8240 is addressed as a slave, an acknowledge is always sent. 0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock bit after receiving one byte of data.
Page 406: I2Csr Field Descriptions—Offset 0X0_300C
C bus is busy. Arbitration lost. This bit is automatically set when the arbitration procedure is lost. Note that the MPC8240 does not automatically retry a failed transfer attempt. 0 Arbitration is not lost. Can only be cleared by software.
Page 407: Programming Guidelines
I C bus protocol behavior. Example I C code can be found in the MPC8240 Device Driver Toolbox available through the PowerPC web site: www.mot.com/SPS/PowerPC/teksupport/faqsolutions/code (using the ‘code samples’ link for the Dink drivers directory).
Page 408: Initialization Sequence
10.4.2 Generation of START After initialization, the following sequence can be used to generate START: 1. If the MPC8240 is connected to a multimaster I C system, test the state of I2CSR[MBB] to check whether the serial bus is free (I2CSR[MBB] = 0) before switching to master mode.
Page 409: Generation Of Stop
STOP condition must ﬁrst be generated by the MPC8240. The MPC8240 automatically generates a STOP if I2CCR[TXAK] = 1. Therefore, I2CCR[TXAK] must be set to a 1 before allowing the MPC8240 to receive the last data byte on the I C bus.
Page 410: Slave Mode Interrupt Service Routine
C by setting I2CCR to 0xA0. 3. Read the I2CDR. 4. Return the MPC8240 to slave mode by setting I2CCR to 0x80. 10.4.7 Slave Mode Interrupt Service Routine In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling of its own address has just been received.
Page 411 Programming Guidelines Clear I2CSR[MIF] == 1 == 0 I2CCR[MSTA] == 0 I2CCR[MTX] == 1 == 1 == 0 Master Xmit I2CCR[MAL] Last byte == 1 Clear I2CCR[MAL] I2CSR[MAAS] == 1 I2CSR[RXAK] == 1 == 0 == 0 I2CSR[MAAS] == 0 Generate End of address phase for STOP...
Page 412 Programming Guidelines 10-18 MPC8240 Integrated Processor User’s Manual...
Page 413: Epic Unit Overview
The interrupt sources and soft reset controlled by the EPIC unit, the sreset signal, and the internal mcp generated by the MPC8240 central control unit (CCU) all cause exceptions in the processor core. The int signal is the main interrupt output from the EPIC to the processor core and causes the external interrupt exception.
Page 414: Epic Features Summary
EPIC Unit Overview 11.1.1 EPIC Features Summary The EPIC unit of the MPC8240 implements the following features: • OpenPIC programming model • Support for ﬁve external interrupt sources or one serial-style interrupt (16 interrupt sources) • Four global, cascadable, high-resolution timers that can be interrupt sources •...
Page 415: Epic Block Diagram
MPC8240’s internal dma0, dma1, MU, or I C units. 11.1.3 EPIC Block Diagram The EPIC unit in the MPC8240 is accessible from the processor only. The processor reads and writes the conﬁguration and status registers of EPIC. These registers are memory mapped.
Page 416: Epic Register Summary
Global timer 0 destination register (GTDR0) 0x4_1140 Global timer 1 current count register (GTCCR1) T (toggle), COUNT 0x4_1150 Global timer 1 base count register (GTBCR1) CI, BASE_COUNT 0x4_1160 Global timer 1 vector/priority register (GTVPR1) M, A, PRIORITY, VECTOR 11-4 MPC8240 Integrated Processor User’s Manual...
Page 417: Configuration Registers
EPIC Register Summary Table 11-2. EPIC Register Address Map—Global and Timer Registers (Continued) Address Offset Register Name Field Mnemonics from EUMBBAR 0x4_1170 Global timer 1 destination register (GTDR1) 0x4_1180 Global timer 2 current count register (GTCCR2) T (toggle), COUNT 0x4_1190 Global timer 2 base count register (GTBCR2) CI, BASE_COUNT 0x4_11A0...
Page 418 DMA Ch0 interrupt destination register (IIDR1) 0x5_1060 DMA Ch1 interrupt vector/priority register (IIVPR2) M, A, PRIORITY, VECTOR 0x5_1070 DMA Ch1 interrupt destination register (IIDR2) 0x5_1080–0x5_10B0 Reserved — 0x5_10C0 Message unit interrupt vector/priority register M, A, PRIORITY, VECTOR (IIVPR3) 11-6 MPC8240 Integrated Processor User’s Manual...
Page 419: Epic Unit Interrupt Protocol
EPIC Unit Interrupt Protocol Table 11-3. EPIC Register Address Map—Interrupt Source Configuration Registers (Continued) Address Offset Register Name Field Mnemonics from EUMBBAR 0x5_10D0 Message unit interrupt destination register (IIDR3) 0x5_10E0–0x5_FFF0 Reserved — Table 11-4. EPIC Register Address Map—Processor-Related Registers Address Offset Register Name Field Mnemonics from EUMBBAR...
Page 420: Interrupt Acknowledge
• int is asserted when there is an illegal clock ratio value in the EPIC interrupt conﬁguration register. When there is a spurious interrupt, the interrupt handler should not write to the EOI register. Otherwise, a previously accepted interrupt might be cleared unintentionally. 11-8 MPC8240 Integrated Processor User’s Manual...
Page 421: Internal Block Diagram Description
EPIC Unit Interrupt Protocol 11.3.6 Internal Block Diagram Description The internal block diagram shown in Figure 11-2 shows the interaction of the non-programmable EPIC registers and the interrupt delivery logic (assertion of the int signal to the processor). Interrupt sources: serial internal timers direct Interrupt pending register...
Page 422: Interrupt Request Register (Irr)
The pass-through mode is controlled by the GCR[M] bit (enabled when GCR[M] = 0). Note that when switching the EPIC unit from pass-through to mixed mode (either direct or serial), the programming note in Section 11.8, “Programming Guidelines,” may apply. 11-10 MPC8240 Integrated Processor User’s Manual...
Page 423: Epic Direct Interrupt Mode
16 cycles in which to request an interrupt. The serial interrupt interface is clocked by the EPIC S_CLK output. This clock can be programmed to run at 1/2 to 1/14 of the MPC8240’s SDRAM_CLK frequency by appropriately setting a 3-bit ﬁeld in the serial interrupt conﬁguration register.
Page 424: Serial Interrupt Timing Protocol
ﬁrst clear the interrupt from the source before executing any other necessary read or write transactions to service the interrupt device. In any case, the delay should be no less than 16 serial clocks after clearing the interrupt at the source device. 11-12 MPC8240 Integrated Processor User’s Manual...
Page 425: Epic Timers
EPIC Timers 11.7 EPIC Timers The MPC8240 has appropriate clock prescalers and synchronizers to provide a time base for the four global timers (0–3) of the EPIC unit. The global timers can be individually programmed to generate interrupts to the processor when they count down to zero and can be used for system timing or to generate regular periodic interrupts.
Page 426 6. Perform a software loop to clear all pending interrupts: — Load counter with FPR[NIRQ]. — While (counter > 0), perform IACK and EOI’s to guarantee all the interrupt pending and in-service registers are cleared. 7. Set the PCTPR value to desired priority. 11-14 MPC8240 Integrated Processor User’s Manual...
Page 427 Programming Guidelines Depending on the interrupt system conﬁguration, the EPIC unit may generate false interrupts to clear out interrupts either latched during power-up or due to resetting the EPIC unit. A spurious or real vector will be returned for an interrupt acknowledge cycle. See programming note below for the cases that return a real interrupt vector for a false interrupt.
Page 428: Feature Reporting Register (Frr)
0x017 Number of interrupts. This ﬁeld contains the maximum number of interrupt sources supported. In the MPC8240, there are a maximum of 24 interrupts in use at one time: the 4 internal sources (I C, DMA (2), and MU), 4 timer sources and 16 external sources.
Page 429: Epic Interrupt Configuration Register (Eicr)
Register Deﬁnitions Table 11-6 describes the bit settings for the GCR. Table 11-6. GCR Field Descriptions—Offset 0x4_1020 Reset Bits Name Description Value Reset EPIC unit. Writing a one to this bit resets the EPIC controller logic. This bit is cleared automatically when this reset sequence is complete. Setting this bit causes the following: •...
Page 430: Epic Vendor Identification Register (Evi)
Note that an illegal value could result in spurious vectors returned when in either direct or serial mode. Serial interrupt enable. This bit selects whether the MPC8240 IRQ signals are conﬁgured for direct interrupts or serial interrupts. The GCR[M] must be set to 1 (mixed-mode) in order for this bit value to have meaning.
Page 431: Processor Initialization Register (Pi)
Register Deﬁnitions 11.9.5 Processor Initialization Register (PI) The processor initialization register (PI) provides a mechanism for the software, through the EPIC unit, to cause a soft reset of the processor by asserting the sreset signal. Note that this register is read/write. Figure 11-8 shows the bits in the PI. Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11-8.
Page 432: Global Timer Registers
ﬁrmware. The ﬁrmware can use information stored in the HID1 register and information about the actual processor frequency to determine the SDRAM_CLK frequency. However, in some cases, more system frequency information may be required. 11-20 MPC8240 Integrated Processor User’s Manual...
Page 433: Global Timer Current Count Registers (Gtccrs)
Register Deﬁnitions 11.9.7.2 Global Timer Current Count Registers (GTCCRs) The GTCRRs contain the current count for each of the four EPIC timers. Note that these registers are read-only. The address offsets from EUMBBAR for the GTCCRs are described in Table 11-12. Table 11-12.
Page 434: Global Timer Vector/Priority Registers (Gtvprs)
0 0 0 0 0 0 0 0 0 0 PRIORITY 0 0 0 0 0 0 0 0 VECTOR 31 30 29 20 19 16 15 Figure 11-13. Global Timer Vector/Priority Register (GTVPR) 11-22 MPC8240 Integrated Processor User’s Manual...
Page 435: Global Timer Destination Registers (Gtdrs)
11.9.7.5 Global Timer Destination Registers (GTDRs) Each GTDR indicates the destination for the timer’s interrupt. Because the MPC8240’s EPIC unit supports a single processor, the destination is always P0. Note that this register is read-only. The address offsets from EUMBBAR for the GTDRs are described in Table 11-18.
Page 436: External (Direct And Serial), And Internal Interrupt Registers
SVPR1 0x5_0220 SVPR9 0x5_0320 IVPR2 0x5_0240 SVPR2 0x5_0240 SVPR10 0x5_0340 IVPR3 0x5_0260 SVPR3 0x5_0260 SVPR11 0x5_0360 IVPR4 0x5_0280 SVPR4 0x5_0280 SVPR12 0x5_0380 SVPR5 0x5_02A0 SVPR13 0x5_03A0 SVPR6 0x5_02C0 SVPR14 0x5_03C0 SVPR7 0x5_02E0 SVPR15 0x5_03E0 11-24 MPC8240 Integrated Processor User’s Manual...
Page 437: Direct & Serial Interrupt Destination Registers (Idrs, Sdrs)
The IDR and SDR registers indicate the destination for each external interrupt source. Because the MPC8240 is a single-processor device, the destination is always P0. Note that these registers are read-only. The address offsets from EUMBBAR for the IDRs and SDRs are shown in Table 11-22.
Page 438: Direct And Serial Destination Registers (Idr And Sdr)
(IIDRs) The IIDRs have the same format and ﬁeld descriptions as the IDRs (and SDRs), except that they apply to the internal MPC8240 interrupt sources—the I C unit, DMA unit (2 channels), and MU. See Section 11.9.8.2, “Direct & Serial Interrupt Destination Registers (IDRs, SDRs),”...
Page 439: Processor-Related Registers
15 masks all interrupts to the processor. The PCTPR is initialized to 0x0000_000F when the MPC8240 is reset, or when the P0 bit of the processor initialization register is set to one. Note that this register is read/write. Figure 11-17 shows the bits of the PCTPR.
Page 440: Processor End-Of-Interrupt Register (Eoi)
Figure 11-19. Processor End of Interrupt Register (EOI) Table 11-26 shows the bit settings for the EOI. Table 11-26. EOI Field Descriptions—Offset 0x6_00B0 Reset Bits Name Description Value 31–4 — — Reserved 3–0 EOI_CODE — 0000 11-28 MPC8240 Integrated Processor User’s Manual...
Page 441: Powerpc Processor Core
MPC8240. 12.1 Internal Buffers For most operations of the MPC8240, data is latched internally in one of eight data buffers. Each of the eight internal data buffers has a corresponding address buffer. An additional buffer stores the address of the most recent (or current) processor access to local memory.
Page 442: Processor Core/Local Memory Buffers
Figure 12-1. MPC8240 Internal Buffer Organization 12.1.1 Processor Core/Local Memory Buffers Because the MPC8240 has a shared internal data bus between the processor and local memory, for most cases it is unnecessary to buffer data transfers between these devices. However, there is a 32-byte copyback buffer which is used for temporary storage of the following: •...
Page 443: Processor/Pci Buffers
PCI-read-from-local-memory buffer (PCMRB). When the L1 copyback is complete, the data is forwarded to the PCI agent from the PCMRB. The MPC8240 flushes the data in the copyback buffer to local memory at the earliest available opportunity.
Page 444: Processor-To-Pci-Read Buffer (Prprb)
The second reason is that if the target for a processor read from PCI disconnects part way through the data transfer, the MPC8240 may have to handle a local memory access from an alternate PCI master before the disconnected transfer can continue.
Page 445: Processor-To-Pci-Write Buffers (Prpwbs)
Internal Buffers The PCI interface of the MPC8240 continues to request mastership of the PCI bus until the processor’s original request is completed. When the next processor transaction starts, the address is snooped against the address of the previous transaction (in the internal address buffer) to verify that the same cache line is being requested.
Page 446: Pci/Local Memory Buffers
For example, if both PRPWBs are empty and the processor issues a single-beat write to PCI, the data is latched in the ﬁrst buffer and the PCI interface of the MPC8240 requests mastership of the PCI bus for the transfer. The data for the next processor-to-PCI write transaction is latched in the second buffer, even if the second transaction’s address falls...
Page 447: Pci To Local Memory Read Buffering
ﬁrst locked transfer must be snooped so that the cache line in the L1 is invalidated. 12.1.3.1 PCI to Local Memory Read Buffering The following subsections describe the PCMRB buffer and capability of the MPC8240 to perform speculative PCI reads from local memory. 12.1.3.1.1 PCI-to-Local-Memory-Read Buffers (PCMRBs) When a PCI device initiates a read from local memory, the address is snooped on the peripheral logic bus (provided snooping is enabled).
Page 448: Speculative Pci Reads From Local Memory
PCI reads from local memory. When speculative reading is enabled (or a PCI read multiple transfer requests data word 2 of a cache line), the MPC8240 starts the snoop of the next sequential cache-line address. After the speculative snoop response is...
Page 449: Internal Arbitration
The MPC8240 performs arbitration internally for the internal shared processor/memory data bus. Note that all processor-to-PCI transactions are performed strictly in-order with respect to the MPC8240. Also, all snoops for PCI accesses to local memory are performed in order (if snooping is enabled).
Page 450: Dma Transaction Boundaries For Memory/Memory Transfers
PCI latency timer register (PLTR) can affect the streaming of data to the PCI bus. If the latency timer is set to be a shorter period than the time required to transfer 12-10 MPC8240 Integrated Processor User’s Manual...
Page 451: Dma Transaction Boundaries For Pci–Memory Transfers
ﬁrst data beat of a burst from local memory within 16 PCI clock cycles, the transaction is considered to have timed out internally and as a target, the MPC8240 terminates the transaction with a retry. In this case, the CCU continues the access to memory (as a speculative PCI read) in anticipation of the PCI device requesting the same transaction at a later time.
Page 452: Internal Arbitration Priorities
A PCI read from local memory with snoop not complete. See Section 12.2.3, “Guaranteeing Minimum PCI Access Latency to Local Memory.” A low-priority copyback buffer ﬂush A low-priority PCMWB ﬂush A PCMRB prefetch from local memory due to a speculative PCI read operation 12-12 MPC8240 Integrated Processor User’s Manual...
Page 453: Guaranteeing Minimum Pci Access Latency To Local Memory
12.2.3 Guaranteeing Minimum PCI Access Latency to Local Memory On the MPC8240, enabling snooping by clearing PICR2[NOSNOOP_EN] can improve the PCI access latency to local memory by eliminating pipelined processor transactions that have a priority 1.5 in Table 12-2. However, this can also degrade overall system performance by causing all transactions to be snooped on the internal processor bus.
Page 454 Internal Arbitration 12-14 MPC8240 Integrated Processor User’s Manual...
Page 455: Overview
MCP output signal. The system error (SERR) and parity error (PERR) signals are used to report errors on and to the PCI bus. The MPC8240 provides the NMI signal for ISA bridges to report errors on the ISA bus. The MPC8240 internally synchronizes any asynchronous error signals.
Page 456: Error Handling Block Diagram
13.1.2 Priority of Externally Generated Errors and Exceptions Many of the errors detected in the MPC8240 cause exceptions to be taken by the processor core. Table 13-1 describes the relative error priorities.The processor exception generated by each of these conditions is described in Section 5.5, “Exception Model.”...
Page 457: Exceptions And Error Signals
Note that for priority 1 through 5, the exception is the same. The machine check exception and the priority are related to additional error information provided by the MPC8240 (for example, the address provided in the Processor/PCI error address register).
Page 458: Pci Bus Error Signals
PCI bus, bit 14 of the PCI status register is set. Bit 7 of ErrEnR1 enables the reporting (via mcp, if enabled) of SERR assertion by an external agent on the PCI bus. If ErrEnR1[7] = 1 with MPC8240 acting as the initiator, and 13-4...
Page 459: Parity Error (Perr)
Bit 6 of the PCI command register decides whether the MPC8240 ignores PERR. Bit 15 and bit 8 of the PCI status register are used to report when the MPC8240 has detected or reported a data parity error.
Page 460: Processor Interface Errors
These events can mask (or be masked by) other errors until the machine check exception handler clears them. In addition to the error detection bits, the MPC8240 reports the assertion of NMI to the processor core by asserting mcp (if enabled). Note that NMI assertion is not recorded in the MPC8240's error detection bits.
Page 461: Flash Write Error
Not supported See Table 6-9 or Table 6-20 for speciﬁc bit settings. When a processor write parity error occurs, ErrDR2[2] is set. Note that the MPC8240 does not check parity for write transactions to PCI or the local ROM address space.
Page 462: Memory Read Data Parity Error
MPC8240. When a read parity error occurs, ErrDR1[2] is set. The MPC8240 does not check parity for transactions in the local ROM address space. Note that the processor should not check parity for local ROM space transactions because the parity data will be incorrect for these accesses.
Page 463: Memory Select Error
Bit 7 of ErrEnR1 enables the reporting (via mcp, if enabled) of SERR assertion by an external agent on the PCI bus. If ErrEnR1[7] = 1 and the MPC8240 is acting as the initiator and an external PCI agent asserts SERR two clock cycles after the address phase, the error is recorded in bit 7 of ErrDR1 and a machine check is generated to the processor core.
Page 464: Pci Data Parity Error
MPC8240 is the master and detects the assertion of PERR by the target (for a write). If the MPC8240 is acting as a PCI target when the data parity error occurs (on a write), the MPC8240 asserts PERR and sets ErrDR1[6] (PCI target PERR). If the data has been transferred, the MPC8240 completes the operation but discards the data.
Page 465: Nmi (Nonmaskable Interrupt)
Exception Latencies 13.3.3.5 NMI (Nonmaskable Interrupt) If PICR1[MCP_EN] is set and a PCI agent asserts the NMI signal to the MPC8240, the MPC8240 reports the error to the processor core by asserting mcp provided PICR1[MCP_EN] is set. When the NMI signal is asserted, no error ﬂags are set in the status registers of the MPC8240.
Page 466 Exception Latencies 13-12 MPC8240 Integrated Processor User’s Manual...
Page 467: Overview
Chapter 14 Power Management A key feature of the MPC8240 and its predecessor, the MPC603e microprocessor, is that they are designed for low-power operation. The MPC8240 provides both automatic and program-controllable power reduction modes for progressive reduction of power consumption. This chapter describes the support features provided by the MPC8240 for power management of both the processor core and the peripheral logic.
Page 468: Dynamic Power Management
MPC8240 into the full-power state. The MPC8240 in doze mode maintains the PLL in a fully powered state and is locked to the internal sys_logic_clk signal so a transition to the full-power state occurs within four processor clock cycles.
Page 469: Programmable Processor Power Modes
PLL and the internal sys_logic_clk signal. The MPC8240 returns to the full-power state from sleep mode upon receipt of an interrupt (signalled by the assertion of int), a system management interrupt, a hard or soft reset, or any machine check exception.
Page 470: Processor Power Management Modes—Details
Processor Core Power Management 14.2.3 Processor Power Management Modes—Details The following sections describe the characteristics of the MPC8240 power management modes, the requirements for entering and exiting the various modes, and the system capabilities provided by the processor core while the power management modes are active.
Page 471: Processor Nap Mode
When the peripheral logic block has ensured that snooping is no longer necessary, it allows the processor to enter the nap (or sleep) mode and it causes the assertion of the MPC8240 QACK output signal for the duration of the nap mode period.
Page 472: Processor Sleep Mode
Due to the fully static design of the MPC8240, internal processor state is preserved when no internal clock is present. Because the time base and decrementer are disabled while the processor is in sleep mode, the time base contents must be updated from an external time base following sleep mode if accurate time-of-day maintenance is required.
Page 473: Peripheral Logic Power Management
14.3 Peripheral Logic Power Management Similar to the power management features of the processor core, the peripheral logic block of the MPC8240 has its own doze, nap and sleep modes. They are described in the following subsections. The three programmable power saving modes provide different levels of power savings.
Page 474: Peripheral Logic Power Modes Summary
The MPC8240 does not support the broadcast of PCI special cycles related to low-power operation. Thus, the PMCR1[NO_NAP_MSG] and PMCR1[NO_SLEEP_MSG] bits must be set by initialization software (they are cleared upon reset) to indicate that the MPC8240 does not broadcast the HALT or sleep message commands on the PCI bus before entering the nap or sleep modes, respectively.
Page 475: Peripheral Power Management Modes
14.3.2.1 Peripheral Logic Full Power Mode The default power state of the MPC8240 is full-power. In this state, the peripheral logic block is fully powered, and the internal functional units are operating at full clock speed. 14.3.2.2 Peripheral Logic Doze Mode The doze mode is entered when PMCR1[DOZE] and PMCR1[PM] are set and there are no pending operations for the MPC8240.
Page 476: Pci Transactions During Nap Mode
Note that if the MPC8240 is temporarily awakened to service a PCI transaction, the processor core does not respond to any snoop cycles. Software should, therefore, ﬂush the...
Page 477: System Memory Refresh During Sleep Mode
If LP_REF_EN is cleared, the refresh operations stop when the MPC8240 enters the sleep mode. When the MPC8240 is in the sleep state using CBR refresh and keeping the PLL in locked operation, the wake-up latency is comparable to that of nap mode (within four processor clock cycles).
Page 478 # need nop every second inst to make #code read and execute in program order (up until the isync). r0,0x05fc,r0 mfmsr r0,r0,r0 r0,r0,0x0001 # force big endian LE bit r0,r0,r0 xori r0,r0,0x0001 # force big endian LE bit r0,r0,r0 14-12 MPC8240 Integrated Processor User’s Manual...
Page 479 Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes mtmsr r0,r0,r0 isync r0,r0,r0 # save off additional registers to be corrupted r20,0x05f4,r0 mfspr r21, srr0 # put srr0 in r21 r21,0x05f0,r0 # put r21 in 0x05f0 mfspr r22, srr1 # put srr1 in r22 r22,0x05ec,r0 # put r22 in 0x05ec...
Page 480 Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes mtmsr r0,r0,r0 isync r0,r0,r0 # save off additional registers to be corrupted r20,0x05f4,r0 r21,0x05f0,r0 r22,0x05ec,r0 r23,0x05e8,r0 mfcr r23,0x05e4,r0 r0,r0,r0 # restore corrupted registers r23,0x05e4,r0 mtcrf 0xff,r23 r23,0x05e8,r0 r22,0x05ec,r0 r21,0x05f0,r0 r20,0x05f4,r0 r0,0x05fc,r0 sync #****************************************************************** 14-14 MPC8240 Integrated Processor User’s Manual...
Page 481: Debug Register Summary
ECC or parity error • JTAG/testing support 15.1 Debug Register Summary The only debug registers in the MPC8240 are the six memory data path diagnostic registers consisting of three error injection mask registers and three error capture monitor registers. mapped as follows: •...
Page 482: Address Attribute Signals
15.2.1 Memory Address Attribute Signals (MAA[0:2]) The memory attribute signals are associated with the memory interface and provide information about the source of the memory operation being performed by the MPC8240. The encodings of the memory address attribute signals are deﬁned in Table 15-3.
Page 483: Memory Address Attribute Signal Timing
15.2.3 PCI Address Attribute Signals The PCI address attribute signals provide information about the source of the PCI operation being performed by the MPC8240, and the encodings are deﬁned in Table 15-4. Table 15-4. PCI Attribute Signal Encodings PMAA0...
Page 484: Pci Address Attribute Signal Timing
The PCI attribute signals have timing characteristics as shown in Figure 15-1 and Figure 15-2. Note that the attribute signals are valid at the same time as the address for all MPC8240-sourced PCI accesses. During all other clock cycles, PMAA[0:2] are held at the value 0b111.
Page 485: Memory Debug Address
Memory Debug Address PCI_CLK[0:4] AD[31:0] ADDR DATA1 DATA2 DATA3 DATA4 C/BE[3:0] CMD Byte Enables 1 Byte Enables 2 Byte Enables 3 BEs 4 FRAME IRDY DEVSEL TRDY PMAA[0:2] b’111’ VALID Figure 15-2. Example PCI Address Attribute Signal Timing for Burst Write Operations 15.3 Memory Debug Address When enabled, the debug address gives software disassemblers a simple way to reconstruct...
Page 486: Debug Address Signal Definitions
RAS[0:7] shown in the ﬁgures is described in Section 15.3.4, “RAS Encoding.” Reserved Encoded version of RAS[0:7] SDMA[7:0] of column address DA[15:0] 0 0 0 31 30 29 27 26 11 10 9 Figure 15-3. 64-Bit Mode, DRAM and SDRAM Physical Address for Debug 15-6 MPC8240 Integrated Processor User’s Manual...
Page 487: Ras Encoding
Memory Debug Address Reserved Encoded version of RAS[0:7] SDMA[8:0] of column address DA[15:0] 31 30 29 27 26 11 10 Figure 15-4. 32-Bit Mode, DRAM and SDRAM Physical Address for Debug Reserved 1 1 1 1 1 1 1 1 DA[12:0] AR[7:0] of address 0 0 0...
Page 488: Debug Address Timing
Table 15-7. The MIV signal should be sampled with the rising edge of SDRAM_CLK[0:3]. 15-8 MPC8240 Integrated Processor User’s Manual...
Page 489: Miv Signal Timing
Memory Interface Valid (MIV) Table 15-7. Memory Interface Valid Signal Definition Signal Name Pins Active Signal Meaning Indicates that the transaction address or data is valid on the memory bus. 15.4.1 MIV Signal Timing The MIV signal is an active low signal and has timing characteristics as shown in Figure 15-8 through Figure 15-16.
Page 490: Example Fpm Debug Address, Miv, And Maa Timings For Burst Write
2. MIV asserts for address, control, and data on the ﬁrst clock cycle that RAS or CAS is asserted for a write. Figure 15-9. Example FPM Debug Address, MIV, and MAA Timings for Burst Write Operation 15-10 MPC8240 Integrated Processor User’s Manual...
Page 491: Example Edo Debug Address, Miv, And Maa Timings For Burst Read
Memory Interface Valid (MIV) SDRAM_CLK[0::3] RASP RAS/CS[0:7] CAS/DQM[0:7] ADDRESS RHCP DATA DATA0 DATA0 DATA0 DEBUG ADDRESS VALID VALID VALID VALID VALID NOTES 1. Subscripts identify programmable timing variables (RP 1 , RCD 2 , CAS 3 ). 2. MIV asserts for address and control on the ﬁrst clock cycle that RAS or CAS is asserted for a read.
Page 492: Example Edo Debug Address, Miv, And Maa Timings For Burst Write
2. MIV asserts for address, control, and data on the ﬁrst clock cycle that RAS or CAS is asserted for a write. Figure 15-11. Example EDO Debug Address, MIV, and MAA Timings for Burst Write Operation 15-12 MPC8240 Integrated Processor User’s Manual...
Page 493 Memory Interface Valid (MIV) SDRAM CLK[0:3] RAS/CS SDRAS SDCAS ACTORW CAS/DQM ADDRESS SDRAM DATA CAS LATENCY DEBUG VALID ADDRESS VALID Figure 15-12. Example SDRAM Debug Address, MIV, and MAA Timings for Burst Read Operation Chapter 15. Debug Features 15-13...
Page 494 Memory Interface Valid (MIV) SDRAM_ CLK[0:3] RAS/CS SDRAS SDCAS ACTORW CAS/DQM ADDRESS DRAM DATA DEBUG VALID ADDRESS VALID Figure 15-13. Example SDRAM Debug Address, MIV, and MAA Timings for Burst Write Operation 15-14 MPC8240 Integrated Processor User’s Manual...
Page 495: Example Rom Debug Address, Miv, And Maa Timings For Burst Read
Memory Interface Valid (MIV) SDRAM_ CLK[0:3] A[1:0] ROMFAL ROMNAL ROMNAL ROMNAL A[19:2] DATA DATA0 DATA1 DATA2 DATA3 DEBUG VALID VALID VALID VALID ADDRESS VALID NOTES 1. ROMFAL (ROM First Access Latency) = 0–15 clocks. 2. ROMNAL (ROM Nibble Access Latency) = 0–9 clocks. 3.
Page 496 ROMNAL (constant) DEBUG VALID ADDRESS VALID NOTE: 1. V PP multiplexed by system logic with appropriate setup time to write cycle. Figure 15-16. Example Flash Debug Address, MIV, and MAA Timings for Write Operation 15-16 MPC8240 Integrated Processor User’s Manual...
Page 497: Memory Data Path Error Injection/Capture
Memory Data Path Error Injection/Capture 15.5 Memory Data Path Error Injection/Capture The MPC8240 provides hardware to exercise and debug the on-chip ECC and parity logic by allowing the user to inject multi-bit stuck-at faults onto the peripheral logic or memory data/parity buses and to capture the data/parity upon the receipt of an ECC or parity error.
Page 498: Dl Error Injection Mask Register
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAR[7:0] 10 9 Figure 15-20. Parity Error Injection Mask (MDP_ERR_INJ_MASK_PAR)— Offsets 0xF_F008, 0xF08 15-18 MPC8240 Integrated Processor User’s Manual...
Page 499: Memory Data Path Error Capture Monitor Registers
Memory Data Path Error Injection/Capture Table 15-10. Parity Error Injection Mask Bit Field Definitions Bits Name Reset Value Description 31–8 — all 0s Read Reserved RD_EN Memory data path read enable bit 0 Disables error injection for reads 1 Enables error injection onto the peripheral logic data bus during reads from local memory WR_EN Memory data path write enable bit...
Page 500: Dl Error Capture Monitor Register
Bits Name Reset Value Description 31–9 — all 0s Read Reserved FLAG Capture ﬂag 0 No data captured 1 Data valid 7–0 DPAR[7:0] 0b0000_0000 Read Capture monitor for memory data path data parity bus 15-20 MPC8240 Integrated Processor User’s Manual...
Page 501: Jtag/Testing Support
JTAG/Testing Support 15.6 JTAG/Testing Support The MPC8240 provides a joint test action group (JTAG) interface to facilitate boundary-scan testing. The JTAG interface complies to the IEEE 1149.1 boundary-scan speciﬁcation. For additional information about JTAG operations, refer to the IEEE 1149.1 speciﬁcation.
Page 502: Jtag Registers And Scan Chains
The bypass register is a single-stage register used to bypass the boundary-scan latches of the MPC8240 during board-level boundary-scan operations involving components other than the MPC8240. The use of the bypass register reduces the total scan string size of the boundary-scan test.
Page 503: Watchpoint Facility Signal Interface
Chapter 16 Programmable I/O and Watchpoint The MPC8240 programmable I/O and watchpoint facility allows system designers to monitor the state of the internal peripheral logic (interface between the processor core and the peripheral logic block) bus and trigger an output signal as shown in Figure 16-1. The user programs up to two sets of fully maskable 58-bit triggers called watchpoints on the peripheral logic address and control buses.
Page 504: Watchpoint Interface Signal Description
Watchpoint Interface Signal Description • Two watchpoints with 58-bit triggers (signal-by-signal comparison on peripheral logic address and control bus) that control a single TRIG_OUT signal. • TRIG_IN signal for explicitly enabling and disabling the watchpoint facility and for exiting hold state •...
Page 505: Watchpoint Registers
#1 and another for watchpoint #2. In addition, the watchpoint control register is used to conﬁgure the debug address function of the MPC8240 The watchpoint registers are accessible from either the local bus or the PCI bus. The WP_CONTROL[WP_RUN] bit is the only bit that can be changed while the watchpoint facility is enabled (while WP_RUN = 1).
Page 506: Watchpoint Trigger Registers
Watchpoint Registers 16.2.2 Watchpoint Trigger Registers Watchpoint triggers are set based on a subset of the peripheral logic bus that includes the 32-bit address bus and 26 control signals. These watchpoints are compared with the values on the peripheral logic bus on every clock cycle. There are separate sets of trigger registers for watchpoints #1 and #2.
Page 507 Watchpoint Registers Table 16-3. Watchpoint Control Trigger Register Bit Field Definitions (Continued) Bits Name Reset Value Description 20–16 TT[0:4] 0b0_0000 Trigger match condition for TT[0:4] setting on peripheral logic bus TBST_ 0 Trigger if TBST asserted on peripheral logic bus 1 Trigger if TBST negated 14–12 TSIZ[0:2]...
Page 508: Watchpoint Mask Registers
Watchpoint Registers Table 16-4 shows the bit deﬁnitions for WP1_ADDR_TRIG and WP2_ADDR_TRIG. Table 16-4. Watchpoint Address Trigger Register Bit Field Definitions Bits Name Reset Value Description 31–0 A[31:0] all 0s Trigger value for peripheral logic address bus 16.2.3 Watchpoint Mask Registers The watchpoint trigger masks are bit-wise ANDed with the corresponding watchpoint trigger bits that have been compared with the current state of the peripheral logic address and control buses to detect watchpoint matches as shown in Figure 16-6.
Page 509: Watchpoint Control Mask Register Bit Field Definitions
Watchpoint Registers 0000_00 TT0[0:4] TSIZ[0:2] 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Figure 16-8. Watchpoint #2 Control Mask Register (WP2_CNTL_MASK)— Offsets 0xF_F038, 0xF38 Table 16-5 shows the bit deﬁnitions for WP1_CNTL_MASK and WP2_CNTL_MASK. Table 16-5.
Page 510: Watchpoint Control Register (Wp_Control)
Watchpoint Registers Table 16-5. Watchpoint Control Mask Register Bit Field Definitions (Continued) Bits Name Reset Value Description INT_ R/W 0 Ignore INT_ trigger bit in WPx_CNTL_TRIG. 1 Compare INT on peripheral logic bus with WPx_CNTL_TRIG bit. MCP_ R/W 0 Ignore MCP_ trigger bit in WPx_CNTL_TRIG. 1 Compare MCP on peripheral logic bus with WPx_CNTL_TRIG bit.
Page 511: Watchpoint Control Register Bit Field Definitions
Watchpoint Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Figure 16-11. Watchpoint Control Register (WP_CONTROL)— Offsets 0xF_F048, 0xF48 Table 16-7 shows the bit ﬁeld deﬁnitions for WP_CONTROL.
Page 512 Watchpoint Registers Table 16-7. Watchpoint Control Register Bit Field Definitions (Continued) Reset Bits Name Description Value 11–8 WP1_CNT[0–3] 0b0000 The watchpoint #1 counter ﬁeld sets the initial value of the countdown counter for watchpoint #1. This counter is used in all watchpoint operation modes.
Page 513: Watchpoint Mode Select (Wp_Control[Wp_Mode])
Watchpoint Registers Table 16-8. Watchpoint Mode Select (WP_CONTROL[WP_MODE]) Watchpoint Watchpoint Watchpoint Watchpoint WP_MODE Deﬁnition [0–1] Trigger (T Counter (C Trigger (T Counter (C Single mode √ √ Assert TRIG_OUT after C occurrence of the unmasked trigger parameters for watchpoint #1. Waterfall mode √...
Page 514: State And Block Diagrams
State and Block Diagrams 16.3 State and Block Diagrams Figure 16-12 shows a state diagram of the watchpoint facility. resume & !wp_cont !match !wp_run resume & match & wp_cont !wp_cont & IDLE !wp_trig_hold COMPARE HOLD !resume wp_run match & wp_trig_hold !wp_run match &...
Page 515: Watchpoint Trigger Applications
Watchpoint Trigger Applications Figure 16-13 shows a block diagram of the watchpoint facility. WP1_TRIGGER WP1_MASK Counter 1 MATCH1 WP2_TRIGGER WP2_MASK Counter 2 MATCH2 wp1_cnt Watchpoint WP_CONTROL wp2_cnt controller wp_control wp_run TRIG_OUT Figure 16-13. Watchpoint Facility Block Diagram 16.4 Watchpoint Trigger Applications The watchpoint facility output trigger can be used by the system designer to initiate a halt to the processor core through the checkstop signals.
Page 516 Watchpoint Trigger Applications 16-14...
Page 517: A.1 Address Space For Map A
Appendix A Address Map A The MPC8240 supports two address maps. The preferred address map, map B, is described in Chapter 3, “Address Maps.” This appendix describes address map A. Address map A conforms to the now-obsolete PowerPC reference platform (PReP) speciﬁcation.
Page 518: A-2 Map A—Pci Memory Master View
Section 7.4.5.2, “Accessing the PCI Conﬁguration Space.” 4. If the ROM is local, the MPC8240 ROM interface handles the access to local ROM. If ROM is remote, then the MPC8240 generates a PCI memory transaction in the range 0xFF00_0000 to 0xFFFF_FFFF.
Page 519: A-1 Processor Core Address Map
Address Space for Map A MPC8240 Memory Controller Processor Reserved Not forwarded to PCI bus. Local Local Memory controller memory space memory performs local cycles memory access Memory select error PCI I/O Space Clears A31 (msb) and I/O addresses PCI bus port...
Page 520: A-2 Pci Memory Master Address Map
(msb) cleared Memory controller memory performs memory cycles cycles. Memory select error 4GB-16MB If ROM is local, then reserved if ROM is remote, then PCI memory space Figure A-2. PCI Memory Master Address Map A MPC8240 Integrated Processor User’s Manual...
Page 521: A-3 Pci I/O Master Address Map
Figure A-3. PCI I/O Master Address Map A A.2 Conﬁguration Accesses Using Direct Method For systems implementing address map A on the MPC8240, there is an alternate method for generating type 0 conﬁguration cycles called the direct access method. For more information about other conﬁguration accesses, see Section 7.4.5.2, “Accessing the PCI...
Page 522: A-4 Direct-Access Pci Configuration Transaction
Therefore, no PCI device should use AD23 for the IDSEL input on systems using address map A. For type 1 translations, the MPC8240 copies the 30 high-order bits of the CONFIG_ADDR register (without modiﬁcation) onto the AD[31:2] signals during the address phase. The MPC8240 automatically translates AD[1:0] into 0b01 during the address phase to indicate a type 1 conﬁguration cycle.
Page 523: B.1 Byte Ordering Overview
The PowerPC architecture deﬁnes two bits in a processor’s machine state register (MSR) for specifying byte ordering—LE (little-endian mode) and ILE (exception little-endian mode). For the MPC8240, these bits control only the addresses generated by Appendix B. Bit and Byte Ordering...
Page 524: B.3 Big-Endian Mode
(MSB to LSB, and so on) and the addresses must be unmunged external to the processor core. When conﬁgured for little-endian mode, the MPC8240 unmunges the address and reverses the byte lanes between the PCI bus and local memory in the central control unit (CCU).
Page 525: B-1 Four-Byte Transfer To Pci Memory Space—Big-Endian Mode
Big-Endian Mode Figure B-1 shows a 4-byte write to PCI memory space in big-endian mode. Core Processor PA[28–31] 0 0 0 0 Byte lanes Internal peripheral logic data bus Runs PCI memory transaction During address phase 0 0 0 0 AD[3–0] (AD[1–0] = 0b00 for memory space access) PCI byte lanes (C/BE[3–0] asserted)
Page 526: B-2 . Big-Endian Memory Image In Local Memory
‘r’ ‘l’ ‘d’ 0x55 Contents Address 0xFE 0xDC 0xBA 0x98 Contents Address Figure B-2. . Big-Endian Memory Image in Local Memory Note that the stored data has big-endian ordering. The ‘h’ is at address 0x000. MPC8240 Integrated Processor User’s Manual...
Page 527: B.4 Little-Endian Mode
Little-Endian Mode If the data is stored to the PCI memory space, it appears as shown in Figure B-3. ‘l’ ‘l’ ‘e’ ‘h’ Contents Address ‘w’ ‘ ’ ‘,’ ‘o’ Contents Address ‘d’ ‘l’ ‘r’ ‘o’ Contents Address 0x55 0x00 Contents Address 0x98...
Page 528: B-2 Processor Address Modification For Individual Aligned Scalars
Only the address is modiﬁed not the byte order. The munged address is used by the memory interface of the MPC8240 to access local memory. To provide true little-endian byte-ordering to the PCI bus, the MPC8240 unmunges the address to its original value and the byte lanes are reversed.
Page 529: B-4 Munged Memory Image In Local Memory
(0d1234) at 0x00E store byte (0x55) at 0x00D If the data is stored to local memory in little-endian mode, the MPC8240 stores the data to the munged addresses in local memory as shown in Figure B-4. ‘w’...
Page 530: B-5 Little-Endian Memory Image In Little-Endian Pci Memory Space
Note that the string ‘hello, world’ starts at address 0x000. The other data is stored to the desired location with true little-endian byte ordering. Figure B-6 through Figure B-11 show the munging/unmunging process for transfers to the PCI memory space and to the PCI I/O space. MPC8240 Integrated Processor User’s Manual...
Page 531: B-6 One-Byte Transfer To Pci Memory Space—Little-Endian Mode
Little-Endian Mode Core Processor A28–A31 0 0 1 0 Munge address XOR with 111 PA[28–31] 0 1 0 1 Byte lanes Internal peripheral logic data bus Unmunges address Swaps byte lanes Runs PCI memory transaction During address phase AD[3–0] 0 0 0 0 (AD[1–0] = 0b00 for memory space access) PCI byte lanes (C/BE2 asserted) PCI data bus (AD[31–0] during data phase)
Page 532: B-7 Two-Byte Transfer To Pci Memory Space—Little-Endian Mode
0 0 0 0 (AD[1–0] = 0b00 for memory space access) PCI byte lanes (C/BE[3–2] asserted) PCI data bus (AD[31–0] during data phase) 0x00 0x08 PCI Memory Space Figure B-7. Two-Byte Transfer to PCI Memory Space—Little-Endian Mode B-10 MPC8240 Integrated Processor User’s Manual...
Page 533: B-8 Four-Byte Transfer To Pci Memory Space—Little-Endian Mode
Little-Endian Mode Core Processor A[28–31] 0 0 0 0 Munge address XOR with 100 PA[28–31] 0 1 0 0 Byte lanes Internal peripheral logic data bus Unmunges address Swaps byte lanes Runs PCI memory transaction During address phase AD[3–0] 0 0 0 0 (AD[1–0] = 0b00 for memory space access) PCI byte lanes (C/BE[3–0] asserted) PCI data bus (AD[31–0] during data phase)
Page 534: B-9 One-Byte Transfer To Pci I/O Space—Little-Endian Mode
During address phase AD[3–0] 0 1 0 1 PCI byte lanes (C/BE1 asserted) PCI data bus (AD[31–0] during data phase) 0x00 0x08 PCI I/O Space Figure B-9. One-Byte Transfer to PCI I/O Space—Little-Endian Mode B-12 MPC8240 Integrated Processor User’s Manual...
Page 535: B-10 Two-Byte Transfer To Pci I/O Space—Little-Endian Mode
Little-Endian Mode Core Processor A[28–31] 0 1 0 0 Munge address XOR with 110 PA[28–31] 0 0 1 0 Byte lanes Internal peripheral logic data bus Unmunges address Swaps byte lanes Runs PCI I/O transaction AD[3–0] 0 1 0 0 During address phase PCI byte lanes (C/BE[1–0] asserted) PCI data bus (AD[31–0] during data phase)
Page 536: B-11 Four-Byte Transfer To Pci I/O Space—Little-Endian Mode
During address phase AD[3–0] 0 1 0 0 PCI byte lanes (C/BE[3–0] asserted) PCI data bus (AD[31–0] during data phase) 0x00 0x08 PCI I/O Space Figure B-11. Four-Byte Transfer to PCI I/O Space—Little-Endian Mode B-14 MPC8240 Integrated Processor User’s Manual...
Page 537: B.4.1 I/O Addressing In Little-Endian Mode
(lhbrx, lwbrx, sthbrx, and stwbrx) may be used. B.5 Setting the Endian Mode of Operation The MPC8240 powers up in big-endian mode. The endian mode should be set early in the initialization routine and remain unchanged for the duration of system operation. To switch between the different endian modes of operation, the processor core must run in serialized mode and the caches must be disabled.
Page 538 Setting the Endian Mode of Operation B-16 MPC8240 Integrated Processor User’s Manual...
Page 539 Initialization Example This appendix contains an example PowerPC assembly language routine for initializing the conﬁguration registers for the MPC8240 using address map B. It is excerpted from DINK32 source code available for download at http://www.motorola.com/semiconductors. DINK32 source code also contains examples on how to initialize the embedded utilities...
Page 540 // snoop wt states = 1 oris r0, r0, 0x0000 // snoop wt states = 0 r0, r0, 0x0004 // addr. phase wt states = 1 r0, r0, 0x0000 // addr. phase wt states = 0 MPC8240 Integrated Processor User’s Manual...
Page 541 r4, r4, r0 stwbrx r4,0,r6 //------ Embedded Unitility Memory Block Base Address Register( eumbbar ) addis r3,r0,BMC_BASE // EUMBBAR (78) = 0xFC00_0000 r3,r3,0x0078 stwbrx r3,0,r5 r4,0xfc00// Don’t forget to map this area stwbrx r4,0,r6 // into the BATs sync //! ===MCCR1=== MEMORY CONTROL CONFIGURATION addis r3,r0,BMC_BASE // MCCR1 (F0) = 0x8800_0000...
Page 542 Set MESAR2 (8c) r3,r3,XMEMSTARTADDR2 stwbrx r3,0,r5 addis r4,r0,0x0000 r4,r4,0x0000 stwbrx r4,0,r6 addis r3,r0,BMC_BASE// Set MEAR1 (90) r3,r3,MEMENDADDR1 stwbrx r3,0,r5 addis r4,r0,0x7f5f r4,r4,0x3f1f// ending address of bank 0 is // 0x0x01FFFFFF stwbrx r4,0,r6 MPC8240 Integrated Processor User’s Manual...
Page 543 addis r3,r0,BMC_BASE// Set MEAR2 (94) r3,r3,MEMENDADDR2 stwbrx r3,0,r5 addis r4,r0,0xffdf r4,r4,0xbf9f stwbrx r4,0,r6 addis r3,r0,BMC_BASE// MEEAR1 (98) = r3,r3,XMEMENDADDR1 stwbrx r3,0,r5 addis r4,r0,0x0000 r4,r4,0x0000 stwbrx r4,0,r6 addis r3,r0,BMC_BASE// MEEAR2 (9c) = r3,r3,XMEMENDADDR2 stwbrx r3,0,r5 addis r4,r0,0x0000 r4,r4,0x0000 stwbrx r4,0,r6 //-------ODCR addis r3,r0,BMC_BASE// Set ODCR r3,r3,0x73...
Page 544 //------ WP1_ADDR_TRIG addis r3,r0,BMC_BASE_HIGH // WP1_ADDR_TRIG (0xFF01C) = r3,r3,0xF01C stwbrx r3,0,r5 addis r4,r0,0x0006 // Set to 0x60000 r4,r4,0x0000 stwbrx r4,0,r6 //------ WP1_CNTL_MASK addis r3,r0,BMC_BASE_HIGH // WP1_CNTL_MASK (0xFF020) = r3,r3,0xF020 stwbrx r3,0,r5 addis r4,r0,0x0000 r4,r4,0x0180 stwbrx r4,0,r6 MPC8240 Integrated Processor User’s Manual...
Page 545 // Enable Watchpoint on seperate write r4,r4,0x01C6 stwbrx r4,0,r6 sync eieio r3, 0x0 r3, r3, r11 // restore MPC8240 Vendor ID /********************************************************** * function: get_eumbbar * output: r3 - content of eumbbar **********************************************************/ .text .align 2 .global get_eumbbar get_eumbbar:...
Page 546 MPC8240 Integrated Processor User’s Manual...
Page 547: D.1 Instructions Sorted By Mnemonic
Appendix D PowerPC Instruction Set Listings This appendix lists the MPC8240 microprocessor’s instruction set as well as the additional PowerPC instructions not implemented in the MPC8240. Instructions are sorted by mnemonic, opcode, function, and form. Also included in this appendix is a quick reference table that contains general information, such as the architecture level, privilege level, and form, and indicates if the instruction is 64-bit and optional.
Page 548 0 0 0 0 0 dcbz 0 0 0 0 0 1014 divdx divdux divwx divwux eciwx ecowx eieio 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPC8240 Integrated Processor User’s Manual...
Page 549 Instructions Sorted by Mnemonic Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eqvx extsbx 0 0 0 0 0 extshx 0 0 0 0 0 extswx 0 0 0 0 0 fabsx...
Page 550 0 0 0 0 0 isync 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lbzu lbzux lbzx ldarx ldux lfdu lfdux lfdx lfsu lfsux lfsx lhau lhaux lhax lhbrx lhzu lhzux lhzx MPC8240 Integrated Processor User’s Manual...
Page 551 Instructions Sorted by Mnemonic Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lswi lswx lwarx lwaux lwax lwbrx lwzu lwzux lwzx mcrf crfD crfS 0 0 0 0 0 mcrfs crfD...
Page 552 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1,4,5 slbie 0 0 0 0 0 0 0 0 0 0 sldx slwx sradx sradix srawx srawix srdx srwx MPC8240 Integrated Processor User’s Manual...
Page 553 Instructions Sorted by Mnemonic Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stbu stbux stbx stdcx. stdu stdux stdx stfd stfdu stfdux stfdx stfiwx stfs stfsu stfsux...
Page 554 0 0 0 0 0 0 0 0 0 0 SIMM xorx xori UIMM xoris UIMM Supervisor-level instruction Supervisor- and user-level instruction Load and store string or multiple instruction 64-bit instruction Optional in the PowerPC architecture Implementation-speciﬁc instruction MPC8240 Integrated Processor User’s Manual...
Page 555: D.2 Instructions Sorted By Opcode
Key: Reserved bits Instruction not implemented in the MPC8240 Table D-2. Complete Instruction List Sorted by Opcode Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
Page 556 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 ldux 0 1 1 1 1 1 0 0 0 0 1 1 0 1 0 1 D-10 MPC8240 Integrated Processor User’s Manual...
Page 557 Instructions Sorted by Opcode Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcbst 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 lwzux 0 1 1 1 1 1...
Page 558 0 1 1 1 1 1 0 0 1 0 mcrxr 0 1 1 1 1 1 crfD 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 D-12 MPC8240 Integrated Processor User’s Manual...
Page 559 Instructions Sorted by Opcode Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lswx 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 1 lwbrx 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0...
Page 560 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 fmulsx 1 1 1 0 1 1 0 0 0 0 0 1 1 0 0 1 D-14 MPC8240 Integrated Processor User’s Manual...
Page 561 Instructions Sorted by Opcode Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fmsubsx 1 1 1 0 1 1 1 1 1 0 0 fmaddsx 1 1 1 0 1 1 1 1 1 0 1...
Page 562 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 Supervisor-level instruction Supervisor- and user-level instruction Load and store string or multiple instruction 64-bit instruction Optional in the PowerPC architecture MPC8240-implementation speciﬁc instruction D-16 MPC8240 Integrated Processor User’s Manual...
Page 563: D.3 Instructions Grouped By Functional Categories
Table D-3 through Table D-30 list the PowerPC instructions grouped by function. Key: Reserved bits Instruction not implemented in the MPC8240 Table D-3. Integer Arithmetic Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
Page 564: D-4 Integer Compare Instructions
UIMM Table D-6. Integer Rotate Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldclx rldcrx rldicx rldiclx D-18 MPC8240 Integrated Processor User’s Manual...
Page 565: D-7 Integer Shift Instructions
Instructions Grouped by Functional Categories Table D-6. Integer Rotate Instructions (Continued) rldicrx rldimix rlwimix rlwinmx rlwnmx Table D-7. Integer Shift Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sldx slwx sradx...
Page 566: D-9 Floating-Point Multiply-Add Instructions7
0 0 0 0 0 mtfsb0x crbD 0 0 0 0 0 0 0 0 0 0 mtfsb1x crbD 0 0 0 0 0 0 0 0 0 0 mtfsfx mtfsfix crfD 0 0 0 0 0 D-20 MPC8240 Integrated Processor User’s Manual...
Page 567: D-13 Integer Load Instructions
Instructions Grouped by Functional Categories Table D-13. Integer Load Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lbzu lbzux lbzx ldux lhau lhaux lhax lhzu lhzux...
Page 568: D-15 Integer Load And Store With Byte-Reverse Instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isync 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ldarx lwarx stdcx. D-22 MPC8240 Integrated Processor User’s Manual...
Page 569: D-19 Floating-Point Load Instructions7
Instructions Grouped by Functional Categories Table D-18. Memory Synchronization Instructions (Continued) stwcx. sync 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table D-19. Floating-Point Load Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lfdu lfdux lfdx...
Page 570: D-22 Branch Instructions
0 0 0 0 0 0 0 0 0 0 mfcr 0 0 0 0 0 0 0 0 0 0 mfmsr 0 0 0 0 0 0 0 0 0 0 mfspr D-24 MPC8240 Integrated Processor User’s Manual...
Page 571: D-27 Cache Management Instructions
Instructions Grouped by Functional Categories Table D-26. Processor Control Instructions (Continued) mftb mtcrf mtmsr 0 0 0 0 0 0 0 0 0 0 mtspr Table D-27. Cache Management Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcbf 0 0 0 0 0 dcbi...
Page 572: D-30 External Control Instructions
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eciwx ecowx Supervisor-level instruction Supervisor- and user-level instruction Load and store string or multiple instruction 64-bit instruction Optional in the PowerPC architecture MPC8240-implementation speciﬁc instruction D-26 MPC8240 Integrated Processor User’s Manual...
Page 573: D.4 Instructions Sorted By Form
Instructions Sorted by Form D.4 Instructions Sorted by Form Table D-31 through Table D-45 list the PowerPC instructions grouped by form. Key: Reserved bits Instruction not implemented in the MPC8240 Table D-31. I-Form OPCD AA LK Speciﬁc Instruction Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AA LK Table D-32.
Page 574 SIMM addic. SIMM addis SIMM andi. UIMM andis. UIMM cmpi crfD SIMM cmpli crfD UIMM lbzu lfdu lfsu lhau lhzu lwzu mulli SIMM UIMM oris UIMM stbu stfd stfdu stfs stfsu sthu stmw stwu D-28 MPC8240 Integrated Processor user’s Manual...
Page 575: D-35 Ds-Form
Instructions Sorted by Form subfic SIMM SIMM SIMM xori UIMM xoris UIMM Table D-35. DS-Form OPCD OPCD Speciﬁc Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stdu Table D-36.
Page 576 0 0 0 0 0 extswx 0 0 0 0 0 fabsx 0 0 0 0 0 fcfidx 0 0 0 0 0 fcmpo crfD fcmpu crfD fctidx 0 0 0 0 0 D-30 MPC8240 Integrated Processor user’s Manual...
Page 577 Instructions Sorted by Form fctidzx 0 0 0 0 0 fctiwx 0 0 0 0 0 fctiw 0 0 0 0 0 fmrx 0 0 0 0 0 fnabsx 0 0 0 0 0 fnegx 0 0 0 0 0 frspx 0 0 0 0 0 icbi...
Page 578 0 0 0 0 0 1,4,5 slbie 0 0 0 0 0 0 0 0 0 0 sldx slwx sradx srawx srawix srdx srwx stbux stbx stdcx stdux stdx stfdux stfdx stfiwx stfsux stfsx sthbrx sthux D-32 MPC8240 Integrated Processor user’s Manual...
Page 579: D-37 Xl-Form
Instructions Sorted by Form sthx stswi stswx stwbrx stwcx stwux stwx sync 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tlbia 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tlbie 0 0 0 0 0 0 0 0 0 0...
Page 580: D-38 Xfx-Form
OPCD OPCD 0 0 0 0 0 Speciﬁc Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx D-34 MPC8240 Integrated Processor user’s Manual...
Page 581: D-42 A-Form
Instructions Sorted by Form addcx addex addmex 0 0 0 0 0 addzex 0 0 0 0 0 divdx divdux divwx divwux mulhdx mulhdux mulhwx mulhwux mulldx mullwx negx 0 0 0 0 0 subfx subfcx subfex subfmex 0 0 0 0 0 subfzex 0 0 0 0 0 Table D-42.
Page 582: D-43 M-Form
Table D-44. MD-Form OPCD OPCD Speciﬁc Instructions Name 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldicx rldiclx rldicrx rldimix D-36 MPC8240 Integrated Processor user’s Manual...
Page 583: D-45 Mds-Form
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldclx rldcrx Supervisor-level instruction Supervisor- and user-level instruction Load and store string or multiple instruction 64-bit instruction Optional in the PowerPC architecture MPC8240-implementation speciﬁc instruction Appendix D. PowerPC Instruction Set Listings D-37...
Page 584: D.5 Instruction Set Legend
D.5 Instruction Set Legend Table D-46 provides general information on the PowerPC instruction set (such as the architectural level, privilege level, and form). Key: Reserved bits Instruction not implemented in the MPC8240 Table D-46. PowerPC Instruction Set Legend UISA Supervisor Level 64-Bit...
Page 585 Instruction Set Legend Table D-46. PowerPC Instruction Set Legend (Continued) UISA Supervisor Level 64-Bit Optional Form crorc √ crxor √ dcbf √ dcbi √ √ dcbst √ dcbt √ dcbtst √ dcbz √ divdx √ √ divdux √ √ divwx √...
Page 586 √ lbzu √ lbzux √ lbzx √ √ √ ldarx √ √ √ √ ldux √ √ √ √ √ lfdu √ lfdux √ lfdx √ √ lfsu √ lfsux √ lfsx √ √ D-40 MPC8240 Integrated Processor User’s Manual...
Page 587 Instruction Set Legend Table D-46. PowerPC Instruction Set Legend (Continued) UISA Supervisor Level 64-Bit Optional Form lhau √ lhaux √ lhax √ lhbrx √ √ lhzu √ lhzux √ lhzx √ √ lswi √ lswx √ √ √ lwarx √ lwaux √...
Page 588 √ rlwinmx √ rlwnmx √ √ √ 1,4,5 slbia √ √ √ √ 1,4,5 slbie √ √ √ √ sldx √ √ slwx √ sradx √ √ sradix √ √ srawx √ srawix √ D-42 MPC8240 Integrated Processor User’s Manual...
Page 589 Instruction Set Legend Table D-46. PowerPC Instruction Set Legend (Continued) UISA Supervisor Level 64-Bit Optional Form srdx √ √ srwx √ √ stbu √ stbux √ stbx √ √ √ stdcx. √ √ stdu √ √ stdux √ √ stdx √...
Page 590 √ √ √ √ xorx √ xori √ xoris √ Supervisor-level instruction Supervisor- and user-level instruction Load and store string or multiple instruction 64-bit instruction Optional in the PowerPC architecture MPC8240-implementation speciﬁc instruction D-44 MPC8240 Integrated Processor User’s Manual...
Page 591: E.1 Powerpc Register Set
Appendix E Processor Core Register Summary This appendix summarizes the register set in the processor core of the MPC8240 as deﬁned by the three programming environments of the PowerPC architecture—the user instruction set architecture (UISA), the virtual environment architecture (VEA), and the operating environment architecture (OEA), as well as the implementation-speciﬁc registers from the...
Page 592: E.1.1 Powerpc Register Set—Uisa
The number to the right of the register name indicates the decimal number that is used in the syntax of the instruction operands to access the register (for example, the number used to access the XER is one). MPC8240 Integrated Processor User’s Manual...
Page 593: E-1 Mpc8240 Processor Programming Model—Registers
TBR 269 Instruction Address External Access Breakpoint Register Register (Optional) IABR SPR 1010 SPR 282 These implementation–specific registers may not be supported by other PowerPC processors or processor cores. Figure E-1. MPC8240 Processor Programming Model—Registers Appendix E. Processor Core Register Summary...
Page 594: E.1.1.1 General-Purpose Registers (Gprs)
Table E-1. Bit Settings for CR0 Field of CR CR0 Bit Description Negative (LT)—This bit is set when the result is negative. Positive (GT)—This bit is set when the result is positive (and not zero). MPC8240 Integrated Processor User’s Manual...
Page 595: E.1.1.3.3 Condition Register Crn Field—Compare Instruction
PowerPC Register Set Table E-1. Bit Settings for CR0 Field of CR (Continued) CR0 Bit Description Zero (EQ)—This bit is set when the result is zero. Summary overﬂow (SO)—This is a copy of the ﬁnal state of XER[SO] at the completion of the instruction. E.1.1.3.2 Condition Register CR1 Field Deﬁnition The bit settings for the CR1 ﬁeld are shown in Table E-2.
Page 596: E.1.1.4 Floating-Point Status And Control Register (Fpscr)
Floating-point invalid operation exception for invalid compare. This is a sticky bit. Floating-point fraction rounded. The last arithmetic or rounding and conversion instruction that rounded the intermediate result incremented the fraction. This bit is not sticky. MPC8240 Integrated Processor User’s Manual...
Page 597 PowerPC Register Set Table E-4. FPSCR Bit Settings (Continued) Bit(s) Name Description Floating-point fraction inexact. The last arithmetic or rounding and conversion instruction either rounded the intermediate result (producing an inexact fraction) or caused a disabled overﬂow exception. This is not a sticky bit. For more information regarding the relationship between FPSCR[FI] and FPSCR[XX], see the description of the FPSCR[XX] bit.
Page 598: E.1.1.5 Xer Register (Xer)
OE = 1 set the OV bit if the result cannot be represented in 64 bits (mulld, divd, divdu) or in 32 bits (mullw, divw, divwu), and clear it otherwise. The OV bit is not altered by compare instructions that cannot overﬂow (except mtspr to the XER, and mcrxr). MPC8240 Integrated Processor User’s Manual...
Page 599: E.1.1.6 Link Register (Lr)
PowerPC Register Set Table E-6. XER Bit Definitions (Continued) Bit(s) Name Description Carry. The carry bit (CA) is set during execution of the following instructions: • Add carrying, subtract from carrying, add extended, and subtract from extended instructions set CA if there is a carry out of the msb, and clear it otherwise. •...
Page 600: E.1.2 Powerpc Vea Register Set—Time Base
32-bit registers—time base upper (TBU) and time base lower (TBL), whose contents are incremented once every four sys_logic_clk cycles on the MPC8240. Note that the time base registers can be accessed by both user- and supervisor-level instructions. In the context of the VEA, user-level applications are permitted read-only access to the TB.
Page 601: E.1.2.2 Computing Time Of Day From The Time Base
Note that the GPRs, LR, CTR, TBL, MSR, DAR, SDR1, SRR0, SRR1, and SPRG0–SPRG3 are 32 bits wide on 32-bit implementations (like the MPC8240). A summary of the PowerPC OEA supervisor-level registers in the MPC8240 follows: Appendix E. Processor Core Register Summary...
Page 602 — Machine status save/restore register 1 (SRR1). The SRR1 register is used to save machine status on exceptions and to restore machine status when an rﬁ instruction is executed. Implementation Note—The 603e and MPC8240 implement the Key bit (bit 12) in the SRR1 register in order to simplify the table search software. E-12...
Page 603: E.1.3.1 Machine State Register (Msr)
EAR (bits 26–31) are used to select a device, the 603e and MPC8240 only implement the low-order 4 bits (bits 28–31). Note that the EAR register and the eciwx and ecowx instructions are optional in the PowerPC architecture and may not be supported in all PowerPC processors that implement the OEA.
Page 604 In most systems, IP is set to 1 during system initialization, and then cleared to 0 when initialization is complete. Instruction address translation 0 Instruction address translation is disabled. 1 Instruction address translation is enabled. Data address translation 0 Data address translation is disabled. 1 Data address translation is enabled. E-14 MPC8240 Integrated Processor User’s Manual...
Page 605: E.1.3.2 Processor Version Register (Pvr)
15 16 Figure E-11. Processor Version Register (PVR) Software can identify the MPC8240’s processor core by reading the processor version register (PVR). The MPC8240’s processor version number is 0x0081; the processor revision level starts at 0x0100 and is incremented for each revision of the chip. This information is useful for data cache ﬂushing routines for identifying the size of the cache...
Page 606: E-12 Upper Bat Register
M Memory coherence Guarded Attempting to write to the W and G bits in IBAT registers causes boundedly-undeﬁned results. — Reserved 30–31 Protection bits for block. This ﬁeld determines the protection for the block. E-16 MPC8240 Integrated Processor User’s Manual...
Page 607: E.1.3.4 Sdr1
PowerPC Register Set Table E-11 lists the BAT area lengths encoded in BAT[BL]. Table E-11. BAT Area Lengths BAT Area BL Encoding Length 128 Kbytes 000 0000 0000 256 Kbytes 000 0000 0001 512 Kbytes 000 0000 0011 1 Mbyte 000 0000 0111 2 Mbytes 000 0000 1111...
Page 608: E.1.3.5 Segment Registers
GPR. That GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory. SPRG2 This register may be used by the operating system as needed. SPRG3 This register may be used by the operating system as needed. E-18 MPC8240 Integrated Processor User’s Manual...
Page 609: E.1.3.7 Dsisr
PowerPC Register Set E.1.3.7 DSISR The 32-bit DSISR is shown in Figure E-17. DSISR Figure E-17. DSISR For information about bit settings, see Chapter 4, “Exceptions,” in the MPC603e User’s Manual. E.1.3.8 Machine Status Save/Restore Register 0 (SRR0) The format of SRR0 is shown in Figure E-18. Reserved SRR0 29 30 31...
Page 610: E.1.3.11 External Access Register (Ear)
The processor core of the MPC8240 includes some implementation-speciﬁc SPRs of the 603e processor that are not deﬁned by the PowerPC architecture. Most of these are described in the MPC603e User’s Manual and are implemented in the MPC8240 as follows: •...
Page 611: E.2.1 Data And Instruction Tlb Miss Address Registers (Dmiss And Imiss)
Implementation-Speciﬁc Registers from 603e E.2.1 Data and Instruction TLB Miss Address Registers (DMISS and IMISS) The DMISS and IMISS registers have the same format as shown in Figure E-22. They are loaded automatically upon a data or instruction TLB miss. The DMISS and IMISS contain the effective page address of the access that caused the TLB miss exception.
Page 612: E.2.3 Primary And Secondary Hash Address Registers (Hash1 And Hash2)
(no location exists in the TLB entry for this bit). The RPA register can be read and written by software. Reserved 0 0 0 WIMG 19 20 22 23 24 25 28 29 30 31 Figure E-25. Required Physical Address Register (RPA) E-22 MPC8240 Integrated Processor User’s Manual...
Page 613: E.2.5 Instruction Address Breakpoint Register (Iabr)
IABR enabled. Setting this bit indicates that the IABR exception is enabled. Reserved E.3 MPC8240-Speciﬁc Registers The hardware implementation-dependent registers (HIDx) are implemented differently in the MPC8240 as described in the following subsections. Appendix E. Processor Core Register Summary E-23...
Page 614: E.3.1 Hardware Implementation-Dependent Register 0 (Hid0)
The processor core’s implementation of HID0 differs from the MPC603e User’s Manual as follows: • Bit 5, HID0[EICE], has been removed • No support for pipeline tracking Figure E-27 shows the MPC8240 implementation of HID0. HID0 can be accessed with mtspr and mfspr using SPR1008. FBIOB SBCLK...
Page 615 In nap mode, the PLL and the time base remain active. Note that the MPC8240 asserts the QACK output signal depending on the power-saving state of the peripheral logic, and not on the power-saving state of the processor core.
Page 616 HID0). 22–23 — Reserved — IFEM bit on some other PowerPC devices This bit is not used in the MPC8240 (and so it is reserved). 25–26 — Reserved FBIOB Force branch indirect on bus 0 Register indirect branch targets are fetched normally 1 Forces register indirect branch targets to be fetched externally.
Page 617: E.3.2 Hardware Implementation-Dependent Register 1 (Hid1)
Negated sys-logic-clk E.3.2 Hardware Implementation-Dependent Register 1 (HID1) The MPC8240 implementation of HID1 is shown in Figure E-28. HID1 can be accessed with mfspr using SPR1009. PLLRATIO 000 0000 0000 0000 0000 0000 0000 Figure E-28. Hardware Implementation Register 1 (HID1) Table E-22 shows the bit deﬁnitions for HID1.
Page 618: E.3.3 Hardware Implementation-Dependent Register 2 (Hid2)
DWLCK Data cache way lock—Useful for locking blocks of data into the data cache for time-critical applications where deterministic behavior is required. Refer to Section 5.4.2.3, “Cache Locking,” for more information. 27–31 — Reserved E-28 MPC8240 Integrated Processor User’s Manual...
Page 619 Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and deﬁnitions included in the glossary are reprinted from IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of Electrical and Electronics Engineers, Inc.
Page 620 (such as aborting the program that caused the exception). The addresses of the exception handlers are deﬁned by a two-word exception vector that is branched to automatically when an exception occurs. Glossary-2 MPC8240 Integrated Processor User’s Manual...
Page 621 Exclusive state. EMI state (E) in which only one caching device contains data that is also in system memory. Execution synchronization. All instructions in execution are architecturally complete before beginning execution (appearing to begin execution) of the next instruction. Similar to context synchronization but doesn't force the contents of the instruction buffers to be deleted and refetched.
Page 622 The instruction stream is stopped at the decode stage and executing instructions are allowed to complete to create a controlled context for instructions that may be affected by out-of-order, parallel execution. See Context synchronization. Glossary-4 MPC8240 Integrated Processor User’s Manual...
Page 623 Scan interface. The 603e’s test interface. Slave. The device addressed by a master device. The slave is identiﬁed in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure. Snooping. Monitoring addresses driven by a bus master to detect the need for coherency actions.
Page 624 Write-through. A memory update policy in which all processor write cycles are written to both the cache and memory. Glossary-6 MPC8240 Integrated Processor User’s Manual...
Page 625 Addressing FPM interface, 6-46 address translation, 3-11 memory interface, 6-3 address translation registers, 3-14 MPC8240 functional block diagram, 1-2 EUMB (embedded utilities memory block), 3-18 MPC8240 integrated processor core, 1-9 inbound PCI address translation, 3-11 peripheral logic block diagram, 1-11...
Page 626 ??–4-18 CDCR (clock driver control) register, 4-20 processor bus error status Central control unit (CCU) registers, 7-30–7-32, 13-6 cache coherency, 5-24 processor interface registers, 4-29 overview, 12-1 processor/PCI error address register, 13-6 Chaining mode Index-2 MPC8240 Integrated Processor User’s Manual...
Page 627 INDEX reserved bits, 4-1 in big-endian mode, 8-14 summary of registers, list, 4-5, 4-8 in chaining mode, 8-12 EUMB registers in little-endian mode, 8-14 local processor control and status registers, 3-18 local memory to local memory transfers, 8-9 peripheral control and status registers, 3-19 local memory to PCI, 8-9 runtime registers, 3-18 modes...
Page 628 Flash interface registers, 2-27, 4-33, 7-30, 13-4 address multiplexing, 6-77 error reporting, 13-6 operation, 6-73 address/data error, 13-9 overview, 6-73 address/data parity errors, 7-19 timing, 6-78 error detection registers, 4-35, 7-30, 13-5 write operations, 6-83 Index-4 MPC8240 Integrated Processor User’s Manual...
Page 629 INDEX write timing, 6-84 HID0 (hardware implementation-dependent 0) Floating-point model registers FE0/FE1 bits, E-15 description, 5-13, E-24 floating-point unit overview, 5-7 doze bit, 14-4 FP arithmetic instructions, D-19 DPM enable bit, 14-4 FP compare instructions, D-20 nap bit, 14-5 FP load instructions, D-23 HID1 (hardware implementation 1) FP move instructions, D-23 register, 5-16, E-27...
Page 630 INTA (interrupt request) signal, 2-15 PCI interface Integer arithmetic instructions, D-17 address bus decoding, 7-11 Integer compare instructions, D-18 address translation, 7-34 Integer load instructions, D-21 address/data parity error, 13-9 Integer logical instructions, D-18 address/data parity errors, 7-19 Index-6 MPC8240 Integrated Processor User’s Manual...
Page 631 IS (interrupt selector) register, 11-9 memory space addressing, 7-12 ISR (in-service) register, 11-10 MPC8240 ITWR (inbound translation window) register, 3-15 MPC8240 as PCI bus master, 7-2 MPC8240 as PCI target, 7-3 nonmaskable interrupt, 13-11 JTAG interface overview, 1-14, 7-1, 7-1...
Page 632 1-18 refresh overflow error, 13-9 MPC8240 ROM interface, 6-73 aligned scalars, address modification, B-6 SDRAM interface, 6-6 MPC8240 as PCI bus master, 7-2 select error, 13-9 MPC8240 as PCI target, 7-3 signal summary, 6-3 Index-8 MPC8240 Integrated Processor User’s Manual...
Page 633 5-2 Parity error capture monitor register, 15-20 processor core differences, 5-34 Parity error injection mask register, 15-18 uses for the MPC8240, 1-5 PARn (data parity/ECC) signals, 2-20 MSR (machine state register) PBCCR (PCI base class code) register, 4-14...
Page 634 (POR), 13-3 block diagram, 1-11 output signal state, 2-7 bus interface, 5-9 SDRAM initialization, 6-16 bus operation, 1-10 PowerPC architecture features list, 1-11 instruction list, D-1, D-9, D-17 major functional units, 1-12 instruction set, 5-18 Index-10 MPC8240 Integrated Processor User’s Manual...
Page 635 4-10, 7-22 cache units, 5-9 configuration registers description, 5-1 error handling registers, 2-27, 13-4 differences with the MPC8240, 5-34 60x/PCI error address register, 4-40 dispatch unit, 5-6 BESR, 4-34, 4-37 execution units, 5-6 ECC single-bit error registers, 4-33...
Page 636 C interface DEC, E-13, E-19 I2CADR, 10-7 DMISS and IMISS, E-21 I2CCR, 10-10 DSISR, E-19 I2CDR, 10-13 EAR (optional), E-20 I2CFDR, 10-8 HASH1 and HASH2, E-22 I2CSR, 10-11 IABR, E-23 O interface MSR, E-13 Index-12 MPC8240 Integrated Processor User’s Manual...
Page 637 INDEX PVR, E-12, E-15 system configuration, 6-14 RPA, E-22 SDRAM_CLK (SDRAM clock outputs) signals, 2-33 SRR0/SRR1, E-19 SDRAM_SYNC_IN (SDRAM feedback clock) SRs, E-18 signal, 2-33 TB, E-13 SDRAM_SYNC_OUT (SDRAM clock synchronize TBL/TBU, E-10 out), 2-33 user-level SDRAS (SDRAM row address strobe) signal, 2-21 FPR0–FPR31, E-4 Segment registers FPSCR, E-6...
Page 638 E-19 PLL_CFG, 2-31 Timeout, PCI transaction, 7-17 TCK (JTAG test clock), 2-31, 15-21 Timer frequency reporting register, 11-20 TDI (JTAG test data input), 2-32, 15-21 TDO (JTAG test data output), 2-32, 15-21 invalidate, D-25 Index-14 MPC8240 Integrated Processor User’s Manual...
Page 639 INDEX TLB management instructions, D-25 TMS (JTAG test mode select) signal, 2-32, 15-21 Transactions error transactions, 7-30 PCI bus fast back-to-back transactions, 7-21 read transactions, 7-14 write transactions, 7-14 PCI transaction termination, 7-17 retry PCI transactions, 7-18 Transfers DMA transfers local memory to local memory, 8-9 local memory to PCI, 8-9 PCI to local memory, 8-9...
Page 640 INDEX Index-16 MPC8240 Integrated Processor User’s Manual...
Page 641: Pci Bus Interface
Overview Signal Descriptions and Clocking Address Maps Configuration Registers Processor Bus Interface MPC107 Memory Interface PCI Bus Interface DMA Controller Message Unit (I C Interface Embedded Programmable Interrupt Controller (EPIC) Central Control Unit Error Handling Power Management Debug Features Programmable I/O and Watchpoint Address Map A Bit and Byte Ordering Initialization Example...
Page 642: Dma Controller
Overview Signal Descriptions and Clocking Address Maps Configuration Registers Processor Bus Interface MPC107 Memory Interface PCI Bus Interface DMA Controller Message Unit (I C Interface Embedded Programmable Interrupt Controller (EPIC) Central Control Unit Error Handling Power Management Debug Features Programmable I/O and Watchpoint Address Map A Bit and Byte Ordering Initialization Example...

Motorola MPC8240 User Manual

Table of Contents

Table of Contents

Chapter 1 Overview

Chapter 2

Chapter 3 Address Maps

Chapter 5 Powerpc Processor Core

Chapter 6

Chapter 8

Chapter 9

Chapter 10

Chapter 11

Chapter 4 Configuration Registers

Chapter 12 Processor Core/Local Memory Buffers

Chapter 13 Error Handling Block Diagram

Chapter 14 Dynamic Power Management

Chapter 15

Chapter 16

Chapter 7 PCI Bus Interface

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Summary of Contents for Motorola MPC8240