Motorola PowerQUICC II MPC8280 Series Reference Manual page 1435

Numerics
603e
features list, 2-3
60x bus
60x-compatible mode
60x-compatible bus mode, 8-3
address latch enable (ALE), 11-12
BUFCMD, 11-45
EAMUX signal, 11-45
MAR, 11-81
overview, 11-107
size calculation, 8-19
60x-to-local bus transaction priority, 11-8
address
arbitration, 8-7
ARTRY, 8-23
operations, 8-7
pipelining, 8-9
timing configuration, 8-25
transfer attribute signals, 8-10
transfer termination, 8-23
bandwidth control on the IDMA channel, 19-13
bus protocol
address pipelining, 8-7
arbitration phase, 8-6
overview, 8-4
split-bus transactions, 8-7
configuration, 8-2
data
asserting TEA, 8-30
data bus arbitration, 8-26
data bus transfers, 8-27
data streaming mode, 8-27
effect of ARTRY assertion, 8-29
normal termination, 8-27
operations, 8-26
port size data bus transfers and PSDVAL
termination, 8-29
data transfers
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alignment, 8-15
burst ordering, 8-14
port size, 8-17
extended transfer mode, 8-20
extended write cycle data bus contents, 8-21
little-endian mode, 8-33
LSDMR register, 11-25
lwarx/stwcx. support, 8-33
MEI protocol, 8-31
memory coherency, 8-31
no-pipeline mode, 8-26
one-level pipeline mode, 8-26
overview, 8-1
pipeline control, 8-26
port size device interfaces, 8-18
processor state signals, 8-33
PSDMR register, 11-22
single-MPC8280 bus mode, 8-2
TBST signal, 8-13
TCn signals, 8-13
terminology, 8-1
TESCRx registers, 11-34
TLBISYNC input, 8-33
TSIZn signals, 8-13
TTn signals, 8-10
60x bus memory controller, see Memory controller
A
AAL1, 32-1
3-step-SN algorithm, 32-21
three states, 32-22
application considerations, 32-46
ATM controller buffers, 32-40
RxBD, 32-40
TxBDs, 32-42
ATM-to-TDM adaptive slip control, 32-16
CES adaptive threshold tables, 32-18
buffer descriptors, 32-38
receive buffer operation, 32-39
Index-1