Motorola PowerQUICC II MPC8280 Series Reference Manual page 634

Freescale Semiconductor, Inc.
Serial Interface IDL Interface Support
activity on the D channel and indicates that the channel is free by asserting L1GRx. The
MPC8280 samples the L1GRx signal when the IDL sync signal (L1RSYNCx) is asserted.
If L1GRx is asserted, the MPC8280 sends the first zero of the opening flag in the first bit
of the D channel. If a collision is detected on the D channel, the physical layer device
negates L1GRx. The MPC8280 then stops sending and retransmits the frame when L1GRx
is reasserted. This procedure is handled automatically for the first two buffers of a frame.
For the primary rate IDL, the MPC8280 supports up to four 8-bit channels in the frame,
determined by the SIx RAM programming. To support more channels, the user can route
more than one channel to each SCC and the SCC treats it as one high-speed stream and store
it in the same data buffers (appropriate only for transparent data). Additionally, the
MPC8280 can be used to assert strobes for support of additional external IDL channels.
The IDL interface supports the CCITT I.460 recommendation for data-rate adaptation since
it separately accesses each bit of the IDL bus. The current-route RAM specifies which bits
are supported by the IDL interface and by which serial controller. The receiver only
receives bits that are enabled by the receiver route RAM. Otherwise, the transmitter sends
only bits that are enabled by the transmitter route RAM and three-states L1TXDx.
15.6.2 IDL Interface Programming
To program an IDL interface, first program SIxMR[GMx] to the IDL grant mode for that
channel. If the receive and transmit sections interface to the same IDL bus, set
SIxMR[CRTx] to internally connect the Rx clock and sync signals to the transmit section.
Then, program the SIx RAM used for the IDL channels to the preferred routing. See
Section 15.4.4, "SIx RAM Programming Example."
Define the IDL frame structure by programming SIxMR[xFSDx] to have a 1-bit delay from
frame sync to data, SIxMR[FEx] to sample on the falling edge, and SIxMR[CEx] to transmit
on the rising edge of the clock. Program the parallel I/O open-drain register so that L1TXDx
is three-stated when inactive; see Section 41.2.1, "Port Open-Drain Registers
(PODRA–PODRD)." To support the D channel, program the appropriate CMXSCR[GRx]
bit, as described in Section 16.4.5, "CMX SCC Clock Route Register (CMXSCR)," and
program the SIx RAM entry to route data to the chosen serial controller. The two definitions
of IDL, 8 or 10 bits, are implemented by simply modifying the SIx RAM programming. In
both cases, L1GRx is sampled while L1TSYNCx is asserted and transferred to the
D-channel SCC as a grant indication.
15-30 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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