Motorola PowerQUICC II MPC8280 Series Reference Manual page 945

Table 29-2. Channel-Specific Parameters for HDLC (continued)
1
Offset Name Width
0x10 TBDFlags Hword TxDB flags, used by the CP (read-only for the user)
0x12 TBDCNT Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
0x14 TBDPTR Word Tx internal data pointer. Points to current absolute data address of channel, used by the
0x18 INTMSK Hword Channel's interrupt mask flag. See Section 29.3.3.1.1, "Interrupt Circular Table Entry
0x1A CHAMR Hword Channel mode register. See Section 29.3.1.3, "Channel Mode Register
0x1C TCRC Word Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only
0x20 RSTATE Word Rx internal state. To start a receiver channel the user must write to RSTATE
0x24 ZDSTATE Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and
0x28 ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
0x2C ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
0x30 RBDFlags Hword RxBD flags, used by the CP (read-only for the user)
0x32 RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
0x34 RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the
0x38 MFLR Hword Maximum frame length register. Defines the longest expectable frame for this channel.
0x3A MAX_CNT Hword Max_length counter, used by the CP (read-only for the user)
0x3C RCRC Word Temp receive CRC, used by the CP (read-only for the user)
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The offset is relative to dual-port RAM (DPRAM) base address + 64*CH_NUM
29.3.1.1 Internal Transmitter State (TSTATE)—HDLC Mode
Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters
associated with SDMA channel accesses (like function code registers) and starts the
transmitter channel.
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for the user)
CP (read-only for the user)
and Interrupt Mask (INTMSK) —AAL1 CES."
(CHAMR)—HDLC Mode."
for the user)
0xHH80_0000. HH is the RSTATE high byte described in Section 29.3.1.4, "Internal
Receiver State (RSTATE)—HDLC Mode."
0x20FFFFE0 for inverted channel)
for the user)
CP (read-only for the user)
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded
and the LG flag is set in the last frame's BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frame's length is considered to be
everything between flags, including CRC. No more data is written into the current buffer
when the MFLR violation is detected.
Chapter 29. Multi-Channel Controllers (MCCs)
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Channel-Specific Parameters
Description
29-7