Motorola PowerQUICC II MPC8280 Series Reference Manual page 1386

2
I C Registers
40.4.3 I C Baud Rate Generator Register (I2BRG)
2
The I 2 C baud rate generator register, shown in Figure 40-8, sets the divide ratio of the I
BRG.
0
Field
Reset
R/W
Addr
Figure 40-8. I
Table 40-3 describes I2BRG fields.
Bits Name
0–7 DIV Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I
of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty
cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled
(I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1) .
2
40.4.4 I C Event/Mask Registers (I2CER/I2CMR)
The I 2 C event register (I2CER) is used to generate interrupts and report events. When an
event is recognized, the I
cleared by writing ones; writing zeros has no effect. Setting a bit in the I
(I2CMR) enables and clearing a bit masks the corresponding interrupt. Unmasked I2CER
bits must be cleared before the CP clears internal interrupt requests. Figure 40-9 shows both
registers.
0
Field
Reset
R/W
Addr
Figure 40-9. I
40-8
Freescale Semiconductor, Inc.
2
C Baud Rate Generator Register (I2BRG)
Table 40-3. I2BRG Field Descriptions
2 C controller sets the corresponding I2CER bit. I2CER bits are
2 3
— TXE
0x11870(I2CER)/0x11874 I2CMR)
2
C Event/Mask Registers (I2CER/I2CMR)
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DIV
1111_1111
R/W
0x11868
Description
4 5
— BSY
0000_0000
R/W
7
2
C clock generator. The output
2 C mask register
6 7
TXB RXB
MOTOROLA
2 C