Motorola PowerQUICC II MPC8280 Series Reference Manual page 1006

FCC Initialization
in the FCCE register sets the FCC event bit in the interrupt pending register; see
Section 4.3.1.4, "SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)."
30.8.3 FCC Status Registers (FCCSx)
Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor
real-time status conditions (flags, idle) on the RXD line. It does not show the status of CTS
and CD; their real-time status is available in the appropriate parallel I/O port (see
Chapter 41, "Parallel I/O Ports").
30.9 FCC Initialization
The FCCs require a number of registers and parameters to be configured after a power-on
reset. The following outline gives the proper sequence for initializing the FCCs, regardless
of the protocol used.
1. Write the parallel I/O ports to configure and connect the I/O pins to the FCCs.
2. Write the appropriate port registers to configure CTS and CD to be parallel I/O
with interrupt capability or to connect directly to the FCC (if modem support is
needed).
3. If the TSA is used, the SI must be configured. If the FCC is used in the NMSI
mode, the CPM multiplexing logic (CMX) must still be initialized.
4. Write the GFMR, but do not write the ENT or ENR bits yet.
5. Write the FPSMR.
6. Write the FDSR.
7. Initialize the required values for this FCC in its parameter RAM.
8. Clear out any current events in FCCE, as needed.
9. Write the FCCM register to enable the interrupts in the FCCE register.
10. Write the SCPRR_H to configure the FCC interrupt priority.
11. Clear out any current interrupts in the SIPNR_L, if preferred.
12. Write the SIMR_L to enable interrupts to the CP interrupt controller.
13. Issue an
INIT TX AND RX PARAMETERS
number).
14. Set GFMR[ENT] and GFMR[ENR].
The first RxBD's empty bit must be set before the
have their ready bits set at any time. Notice that the CPCR does not need to be accessed
after a power-on reset until an FCC is to be used. An FCC should be disabled and reenabled
after any dynamic change in its parallel I/O ports or serial channel physical interface
configuration. A full reset using CPCR[RST] is a comprehensive reset that also can be used.
30-16
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command (with the correct protocol
INIT RX COMMAND
. However TxBDs can
MOTOROLA