Motorola PowerQUICC II MPC8280 Series Reference Manual page 1126

Interworking Functions
closes the current RxBD, discards incoming cells, modifies the receive statistics
accordingly and initiates a restart sequence. The receiver then waits for a cell with a valid
structured pointer to regain synchronization and start receiving incoming cells again.
The MPC8280 supports SRTS clock recovery using an external PLL. The MPC8280 tracks
the SRTS from the four incoming cells and writes the SRTS code to external logic. See
Section 31.16, "SRTS Generation and Clock Recovery Using External Logic." The data
flow for an AAL1 CES receiver is summarized in Figure 32-4.
Unstructured
data format
32.4 Interworking Functions
The MPC8280 supports the interworking of ATM and TDM. The TDM data processing is
done by the MCC and the SI (refer to Chapter 29, "Multi-Channel Controllers (MCCs),"
and Chapter 15, "Serial Interface with Time-Slot Assigner," for further information). The
ATM controller processes the ATM data.
Data forwarding between the ATM controller and the MCC can be done in two ways:
• Automatic data forwarding. This mode enables automatic data forwarding between
AAL1 and transparent mode over a TDM.
• Core intervention. When an MCC receive buffer is full and its RxBD is closed, the
MCC interrupts the core. The core copies the MCC's receive buffer pointer to an
ATM TxBD and sets the ready bit (TxBD[R]). Similarly, when an ATM receive
buffer is full and its RxBD is closed, the core services the ATM controller's interrupt
by copying the ATM receive buffer pointer to an MCC TxBD and setting TxBD[R].
This mode is useful when additional core processing is required.
32-6
Freescale Semiconductor, Inc.
Process payload
Bit count integrity
Cell size
Pointer verification
Valid cell
3-step SN algorithm
Valid SN
SN/SNP verification
AAL1 cell stream
Figure 32-4. AAL1 CES Receiver Data flow
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Valid/dummy/drop
Tag cell Drop cell
Invalid SN
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