Motorola PowerQUICC II MPC8280 Series Reference Manual page 1458

mode selection, 28-3
NMSI connection, receive and transmit, 28-2
parameter RAM
GCI mode, 28-33
overview, 28-6, 28-33
transparent mode, 28-7
UART mode, 28-7
power, saving, 28-11
programming the controller, 28-13
protocol switching, 28-11
reinitializing the receiver, 28-11
reinitializing the transmitter, 28-10
selecting modes, 28-3
sending a break, 28-14
sending a preamble, 28-14
switching protocols, 28-11
transparent mode
features list, 28-23
overview, 28-22
parameter RAM, 28-7
reception process, 28-23
RxBD, 28-28
TxBD, 28-29
UART mode
character mode, 28-13
commands, 28-13
data handling, 28-13
error handling, 28-15
features list, 28-12
features not supported by SMCs, 28-11
frame format, 28-12
message-oriented mode, 28-13
overview, 28-11
parameter RAM, 28-7
programming example, 28-21
reception process, 28-13
RxBD, 28-15
transmission process, 28-12
TxBD, 28-18
Serial mode
parameter RAM configuration, 34-25
Serial peripheral interface (SPI)
block diagram, 39-1
clocking and pin functions, 39-2
commands, 39-14
configuring the SPI, 39-3
features list, 39-2
interrupt handling, 39-20
master mode, 39-3
maximum receive buffer length (MRBLR), 39-12
multi-master operation, 39-5
parameter RAM, 39-12
programming example
master, 39-18
Index-24
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slave, 39-19
programming model, 39-7
RxBD, 39-16
slave mode, 39-5
SPCOM, 39-11
SPIE, 39-10
SPIM, 39-10
SPMODE, 39-7
TxBD, 39-17
SI memory map, 3-22
SI memory map,, 3-14, 3-15, 3-16
SI RAM programming example, 15-14
SI,, lxxxiii
SICR (SIU interrupt configuration register), 4-18
SICR,, 16-7
SIEXR (SIU external interrupt control register), 4-26
Signals
60x bus
TBST, 8-13
TCn, 8-13
TSIZn, 8-13
TTn, 8-10
byte-select signals, 11-79
chip-select signals, 11-78
general-purpose signals, 11-80
IDMA emulation
DACKx, 19-15
DONEx, 19-16
DREQx, 19-15
memory controller
byte-select signals, 11-12
EAMUX, 11-45
PSDVAL, 11-12, 11-62
SDRAM interface signals, 11-34
UPM interface signals, 11-66
UPM signal negation, 11-82
UPWAIT, 11-83
overview, 6-2
SPISEL, 27-26, 27-27
signals, external
description
EXTCLK,, 6-15
SIPMR_H (SIU high interrupt mask register), 4-23
SIPMR_L (SIU low interrupt mask register), 4-24
SIPNR_H (SIU high interrupt pending register), 4-22
SIPNR_L (SIU low interrupt pending register), 4-23
SIPRR (SIU interrupt priority register), 4-19
SIU memory map,, 3-2
SIUMCR (SIU module configuration register), 4-34
SIVEC (SIU interrupt vector register), 4-25
SMC memory map, 3-21
SMC,, 16-1
SMCE (SMC event) register
GCI mode, 28-37
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