Motorola PowerQUICC II MPC8280 Series Reference Manual page 1411

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Table 41-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
PIN
PDIRC = 1 (Output)
PC6
TDM_C1: L1CLKO
1
PC5
FCC2: TxClav
UTOPIA, slave
1
PC4
FCC2: RxEnb
UTOPIA, master
1
PC3
FCC2: TxD[2]
UTOPIA 8
1
PC2
FCC2: TxD[3]
UTOPIA 8
PC1
BRG6: BRGO
PC0
BRG7: BRGO
1
Not available on the MPC8270.
2
Available only when the primary option for this function is not used.
3
MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See
Section 16.4.1, "CMX UTOPIA Address Register (CMXUAR).")
Table 41-8 shows the port D pin assignments.
Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1)
Pin
PDIRD = 1 (Output)
PD31
1
PD30
FCC2: TxEnb
UTOPIA master
MOTOROLA
Freescale Semiconductor, Inc.
Pin Function
PSORC = 0
Default
PDIRC = 0 (Input)
Input
FCC1: CD
GND
1
FCC2: TxClav
GND
UTOPIA, master
1
FCC2: RxEnb
GND
UTOPIA, slave
FCC3: CTS
GND
FCC3: CD
GND
IDMA2: DREQ
GND
IDMA1: DREQ
GND
Pin Function
PSORD = 0
Default
PDIRD = 0 (Input)
Input
SCC1: RXD
GND
1
FCC2: TxEnb
GND
UTOPIA slave
Chapter 41. Parallel I/O Ports
For More Information On This Product,
Go to: www.freescale.com
PSORC = 1
PDIRC = 0 (Input or
PDIRC = 1 (Output)
Inout if Specified)
1
FCC1: RxAddr[2]
FCC1: RxAddr[2]
MPHY, master,
MPHY, slave,
multiplexed polling
multiplexed polling)
FCC1: RxClav1
MPHY, master, direct
FCC2: RxAddr[2]
MPHY, slave,
multiplexed polling
SI2: L1ST3
FCC2: CTS
Strobe
SI2: L1ST4
FCC2: CD
Strobe
IDMA2: DACK
SCC4: CTS
SCC4: CLSN
(secondary option)
IDMA2: DONE
TDM_A2: L1RQ
SPI: SPISEL
(secondary option)
TDM_A2: L1CLKO
SMC2: SMSYN
(secondary option)
PSORD = 1
PDIRD = 0 (Input, or
PDIRD = 1 (Output)
Inout if Specified)
SCC1: TXD
Ports Tables
Default
Input
1,3
GND
1,3
polling
1
GND
GND
GND
2
V
DD
Inout
2
Inout
GND
Default
Input
41-17

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