Motorola PowerQUICC II MPC8280 Series Reference Manual page 1448

features list, 11-3
general-purpose chip-select machine (GPCM)
access termination, external, 11-65
assertion timing, 11-57
common features, 11-6
differences between MPC8xx and MPC8280,
11-66
external access termination, 11-65
implementation differences with UPMs and
SDRAM machine, 11-7
interface signals, 11-55
MPC8xx versus MPC8280, 11-66
OE timing, 11-61
overview, 11-55
programmable wait state configuration, 11-62
PSDVAL, 11-62
read access extended hold time, 11-62
relaxed timing, 11-59
SRAM configuration, 11-56
strobe signal behavior, 11-56
terminating external accesses, 11-65
timing configuration, 11-56
write enable deassertion timing, 11-58
GPLn timing example, 11-73
implementation differences between machines, 11-7
machine selection, 11-6
MAR in 60x-compatible mode, 11-81
new features supported, 11-1
overview, 11-1
page hit checking, 11-9
parity byte select (PBSE), 11-12
parity checking, 11-9
parity generation, 11-9
programming model, 11-14
PSDVAL, 11-12, 11-62
register descriptions, 11-14
SDRAM machine (synchronous DRAM machine)
address multiplexing, 11-40
bank interleaving, 11-39
BSMA bit, 11-40
commands, JEDEC-standard, 11-37
common features, 11-6
configuration example, 11-52
implementation differences with UPMs and
GPCM, 11-7
JEDEC-standard commands, 11-37
MODE-SET command timing, 11-50
overview, 11-34
page mode support, 11-38
parameters
activate-to-read/write interval, 11-42
column address to first data out, 11-43
last data in to precharge, 11-44
last data out to precharge, 11-43
Index-14
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overview, 11-40
precharge-to-activate interval, 11-41
refresh recovery interval (RFRC), 11-44
pipeline accesses, 11-38
power-on initialization, 11-37
read/write transactions supported, 11-49
refresh, 11-50
SDAM bit, 11-40
supported configurations, 11-37
TEA generation, 11-9
UPMs (user-programmable machines)
access times, handling devices, 11-106
address control bits, 11-81
address multiplexing, 11-81
clock timing, 11-71
common features, 11-6
data sample control, 11-82
data valid, 11-82
differences between MPC8xx and MPC8280,
11-85
DRAM configuration example, 11-84
EDO interface example, 11-97
exception requests, 11-71
hierarchical bus interface example, 11-106
implementation differences with SDRAM
machine and GPCM, 11-7
loop control, 11-80
memory access requests, 11-69
memory system interface example, 11-86
MPC8xx versus MPC8280, 11-85
overview, 11-66
programming the UPM, 11-71
RAM array, 11-73
RAM word, 11-74
refresh timer requests, 11-70
register settings, 11-85
requests, 11-68
signal negation, 11-82
signals, 11-66
software requests, 11-71
UPWAIT signal, 11-83
wait mechanism, 11-83
Memory management units (MMUs), 2-9
memory map
BRGs,, 3-17
clocks and reset keys,, 3-5
PIP,, 3-12
Memory maps
cross-reference guide, 3-1
quick reference guide, 3-1
serial communications controllers (SCCs)
HDLC mode, 22-4
serial management controllers (SMCs)
GCI mode, 28-33
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