Motorola PowerQUICC II MPC8280 Series Reference Manual page 1003

Table 30-5. FCC Parameter RAM Common to All Protocols except ATM (continued)
1
Offset Name Width
0x06 MRBLR Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that
0x08 RSTATE Word Receive internal state. The high byte, RSTATE[0–7], contains the function code register;
0x0C RBASE Word RxBD base address (must be divisible by eight). Defines the starting location in the
0x10 RBDSTAT Hword RxBD status and control. Reserved for CP use only.
0x12 RBDLEN Hword RxBD data length. A down-count value initialized by the CP with MRBLR and
0x14 RDPTR Word RxBD data pointer. Updated by the SDMA channels to show the next address in the buffer
0x18 TSTATE Word Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see
0x1C TBASE Word TxBD base address (must be divisible by eight). Defines the starting location in the
0x20 TBDSTAT Hword TxBD status and control. Reserved for CP use only.
0x22 TBDLEN Hword TxBD data length. A down-count value initialized with the TxBD data length and
0x24 TDPTR Word TxBD data pointer. Updated by the SDMA channels to show the next address in the buffer
0x28 RBPTR Word RxBD pointer. Points to the next BD that the receiver transfers data to when it is in idle
MOTOROLA Chapter 30. Fast Communications Controllers (FCCs)
Freescale Semiconductor, Inc.
the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver
can write fewer bytes to the buffer than MRBLR if a condition such as an error or
end-of-frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied
buffers should be at least as large as the MRBLR.
Note that FCC transmit buffers can have varying lengths by programming TxBD[Data
Length], as needed, and are not affected by the value in MRBLR.
MRBLR is not intended to be changed dynamically while an FCC is operating. Change
MRBLR only when the FCC receiver is disabled.
see Section 30.7.1, "FCC Function Code Registers (FCRx)." RSTATE[8–31] is used by
the CP and must be cleared initially.
memory map for the FCC RxBDs. This provides great flexibility in how FCC RxBDs are
partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last
BD in each BD table, the user can select how many BDs to allocate for the receive side of
every FCC. The user must initialize RBASE before enabling the corresponding channel.
Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or
erratic operation occurs.
decremented with every byte written by the SDMA channels.
to be accessed.
Section 30.7.1, "FCC Function Code Registers (FCRx)." TSTATE[8–31] is used by the CP
and must be cleared initially.
memory map for the FCC TxBDs. This provides great flexibility in how FCC TxBDs are
partitioned. By selecting TBASE entries for all FCCs and by setting the W bit in the last
BD in each BD table, the user can select how many BDs to allocate for the transmit side
of every FCC. The user must initialize TBASE before enabling the corresponding channel.
Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or
erratic operation occurs.
decremented with every byte read by the SDMA channels.
to be accessed.
state or to the current BD during frame processing. After a reset or when the end of the
BD table is reached, the CP sets RBPTR = RBASE. Although the user need never write
to RBPTR in most applications, the user can modify it when the receiver is disabled or
when no receive buffer is in use.
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FCC Parameter RAM
Description
30-13