Motorola PowerQUICC II MPC8280 Series Reference Manual page 638

Freescale Semiconductor, Inc.
Serial Interface GCI Support
15.7.1 SI GCI Activation/Deactivation Procedure
In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The
layer 1 device activates the MPC8280 by enabling the clock pulses and by an indication in
the channel 0 C/I channel. The MPC8280 reports to the core (via a maskable interrupt) that
a valid indication is in the SMC RxBD.
When the core activates the line, the data output of L1TXDn is programmed to zero by
setting SIxGMR[STZx]. Code 0 (command timing TIM) is transmitted on channel 0 C/I
channel to the layer 1 device until STZx is reset. The physical layer device resumes the
clock pulses and gives an indication in the channel 0 C/I channel. The core should reset
STZx to enable data output.
15.7.2 Serial Interface GCI Programming
The following sections describe serial interface GCI programming.
15.7.2.1 Normal Mode GCI Programming
The user can program and configure the channels used for the GCI bus interface. First, the
SIxMR register to the GCI/SCIT mode for that channel must be programmed, using the
DSCx, FEx, CEx, and RFSDx bits. This mode defines the sync pulse to GCI sync for
framing and data clock as one-half the input clock rate. The user can program more than
one channel to interface to the GCI bus. Also, if the receive and transmit section are used
for interfacing the same GCI bus, the user internally connects the receive clock and sync
signals to the SIx RAM transmit section, using the CRTx bits. The user should then define
the GCI frame routing and strobe select using the SIx RAM.
When the receive and transmit section uses the same clock and sync signals, these sections
should be programmed to the same configuration. Also, the L1TXDx pin in the I/O register
should be programmed to be an open-drain output. To support the monitor and the C/I
channels in GCI, those channels should be routed to one of the SMCs. To support the D
channel when there is no possibility of collision, the user should clear the SIxMR[GRx] bit
corresponding to the SCC that supports the D channel.
15.7.2.2 SCIT Programming
For interfacing the GCI/SCIT bus, SIxMR must be programmed to the GCI/SCIT mode.
The SIx RAM is programmed to support a 96-bit frame length and the frame sync is
programmed to the GCI sync pulse. Generally, the SCIT bus supports the D channel access
collision mechanism. For this purpose, the user should program the CRTx bits so the
receive and transmit sections use the same clock and sync signals and program the GRx bits
to transfer the D channel grant to the SCC that supports this channel. The received (grant)
bit should be marked by programming the channel select bits of the SIx RAM to 0b0111 for
an internal assertion of a strobe on this bit. This bit is sampled by the SI and transferred to
15-34 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
For More Information On This Product,
Go to: www.freescale.com