Motorola PowerQUICC II MPC8280 Series Reference Manual page 534

Memory System Interface Example Using UPM
CLKIN
A
row
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
cst1 0
cst2 0
cst3 0
cst4 0
bst1 1
bst2 1
bst3 1
bst4 1
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1 -> DLT3 1
g4t3 0
g5t1
g5t3
redo[0]
redo[1]
loop 0
exen 0
amx0 1
amx1 0
na 0
uta 0
todt 0
last 0
RBS
Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of
11-96
Freescale Semiconductor, Inc.
col 1 col 2 col 3
D1 D2 D3
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
0 0 0
0 0 0
RBS+1 RBS+2 RBS+3
CLKIN)
MPC8280 PowerQUICC II Family Reference Manual
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col 4
D4
0 Bit 0
0 Bit 1
1 Bit 2
1 Bit 3
0 Bit 4
0 Bit 5
1 Bit 6
1 Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
1 Bit 18
0 Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
0 Bit 24
0 Bit 25
0 Bit 26
0 Bit 27
0 Bit 28
1 Bit 29
1 Bit 30
1 Bit 31
RBS+4 RBS+5
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