Motorola PowerQUICC II MPC8280 Series Reference Manual page 547

CLKIN
ADDR + ATTR
TS
AACK
DBG
PSDVAL
TA
D
ALE
MA
CS
WE
OE
BADDR[27–28]
Figure 11-84. Pipelined Bus Operation and Memory Access in 60x-Compatible
Figure 11-85 shows the 1-cycle delay for external master access. For systems that use the
60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be
eliminated by setting BCR[EXDD].
MOTOROLA
Freescale Semiconductor, Inc.
Mode
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
External Master Support (60x-Compatible Mode)
02
00 01
03
11-109