Motorola PowerQUICC II MPC8280 Series Reference Manual page 552

L2 Cache Configurations
Figure 12-1. shows a MPC8280 connected to a MPC2605 integrated L2 cache in copy-back
mode.
MPC8280
CPU_BR, CPU_BG, CPU_DBG
TS, TT[0–4], TBST, TSIZ[1–3]
CI, WT, GBL, TA, DBB, TEA
AACK, ARTRY
Memory Controller
12.1.2 Write-Through Mode
In write-through mode, cacheable write operations are performed to both the L2 cache and
to main memory. Since every cacheable write operation goes to the L2 cache and to main
memory, write operation latency is the same as an ordinary memory write transaction. In
12-2
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BR
BG
DBG
TSIZ[0]
(pull down)
L2_HIT
A[0–31]
D[0–63]
SDRAM Main Memory
Figure 12-1. L2 Cache in Copy-Back Mode
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(pull up)
L2BR
L2BG
L2DBG
CPU_BR,CPU_BG,CPU_DBG
TS, TT[0–4], TBST, TSIZ[0–2]]
CI, WT, GBL, TA, DBB, TEA
AACK, ARTRY
L2_CLAIM
A[0–31]
D[0–63]
Latch
MUX
MPC2605
I/O Devices
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