Motorola PowerQUICC II MPC8280 Series Reference Manual page 1450

memory map, 27-13
serial communications controllers (SCCs)
base addresses, 20-15
BISYNC mode, 23-3
overview, 20-13
UART mode, 21-4
serial management controllers (SMCs)
GCI mode, 28-33
overview, 28-6, 28-33
transparent mode, 28-7
UART mode, 28-7
serial peripheral interface (SPI), 39-12
USB controller, 27-13
parameter RAM,, 14-23
Parity byte select (PBSE), 11-12
PCI bridge, 9-1
60x bus arbitration priority, 9-4
60x bus masters, 9-5
address map, 9-23
address decode flow chart, 9-24, 9-25, 9-26
address translation, 9-28
PCI inbound, 9-28
PCI outbound, 9-29
example, 9-27
programming, 9-27
SIU registers, 9-30
arbitration example, 9-23
burst read example, 9-11
burst write example, 9-12
clocking, 9-3
compact PCI hot swap specification support, 9-5
CompactPCI Hot Swap specification support, 9-5
configuration registers, 9-30
memory-mapped configuration registers, 9-31
discard timer control register (PTCR), 9-36
error address capture register (PCI_EACR),
9-43
error control capture register (PCI_ECCR),
9-44
error control register (ECR), 9-42
error data capture register (PCI_EDCR), 9-43
error mask register (EMR), 9-40
error status register (ESR), 9-39
general purpose control register (GPCR), 9-37
inbound base address registers (PIBARx), 9-46
inbound comparison mask registers (PICMRx),
9-47
inbound translation address registers
(PITARx), 9-45
message unit (I2O) registers, 9-33
PCI general control register (PCI_GCR), 9-38
PCI outbound base address registers
(POBARx), 9-34
Index-16
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PCI outbound comparison mask registers
(POCMRx), 9-35
PCI outbound translation address registers
(POTARx), 9-33
PCI bridge, 9-49
BIST control register, 9-57
device ID register, 9-51
general purpose local access base address
registers (GPLABARx), 9-58
Hot Swap control status register, 9-65
initializing the PCI configuration registers,
9-69
PCI bus arbiter configuration register, 9-64
PCI bus base class code register, 9-55
PCI bus cache line size register, 9-56
PCI bus capabilities pointer register, 9-60
PCI bus command register, 9-51
PCI bus function register, 9-63
PCI bus internal memory-mapped registers
base address register (PIMMRBAR), 9-57
PCI bus interrupt line register, 9-61
PCI bus interrupt pin register, 9-61
PCI bus latency timer register, 9-56
PCI bus MAX LAT, 9-62
PCI bus MIN GNT, 9-62
PCI bus programming interface register, 9-54
PCI bus status register, 9-52
PCI configuration register access from core,
9-66
PCI configuration register access in
Big-Endian mode, 9-66, 9-67, 9-68
PCI Hot Swap register block, 9-65
reader type register, 9-57
revision ID register, 9-54
subclass code register, 9-55
subsystem device ID register, 9-60
subsystem vendor ID register, 9-59
vendor ID register, 9-51
DMA controller, 9-90
block diagram, 9-91
descriptors, 9-101
Big Endian mode, 9-102
Little Endian mode, 9-103
operation, 9-91
byte count registers (DMABCRx), 9-99
current descriptor address registers
(DMACDARx), 9-97
destination address registers (DMADARx),
9-99
direct mode, 9-92
DMA chaining mode, 9-92
DMA coherency, 9-93
DMA transfer types, 9-93
halt and error conditions, 9-93
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