Motorola PowerQUICC II MPC8280 Series Reference Manual page 1329

Table 36-8. FPSMR Ethernet Field Descriptions (continued)
Bits Name
15–20 — Reserved, should be zero.
21 CAM CAM address matching
0 Normal operation.
1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.
22 BRO Broadcast address
0 Receive all frames containing the broadcast address.
1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1.
23 — Reserved, should be zero
24–25 CRC CRC selection
0x Reserved.
10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +
X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet specifications.
11 Reserved.
26–31 — Reserved, should be zero
36.18.2 Ethernet Event Register (FCCE)/Mask Register
(FCCM)
The FCCE, shown in Figure 36-7, is used as the Ethernet event register when the FCC
functions as an Ethernet controller. It generates interrupts and reports events recognized by
the Ethernet channel. On recognition of an event, the Ethernet controller sets the
corresponding FCCE bit. Interrupts generated by this register can be masked in the Ethernet
mask register (FCCM).
The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a
bit masks the corresponding interrupt in the FCCE.
The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not
affect bit values. Unmasked FCCE bits must be cleared before the CP clears the internal
interrupt request.
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 36. Fast Ethernet Controller
For More Information On This Product,
Go to: www.freescale.com
Fast Ethernet Registers
Description
36-23