Motorola PowerQUICC II MPC8280 Series Reference Manual page 672

General-Purpose Timer Units
Table 18-2. TGCR2 Field Descriptions (continued)
Bit Name
2 STP 4 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
3 RST4 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
4 GM2 Gate mode for TGATE2. This bit is valid only if the gate function is enabled in TMR3 or TMR4.
0 Restart gate mode. TGATE2 is used to enable/disable the count. The falling edge of TGATE2
enables and restarts the count and the rising edge of TGATE2 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not
restart the count value in TCN.
5 — Reserved, should be cleared.
6 STP3 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, however it is
possible to read the values while the clock is stopped. The clocks to the timer remain stopped
until the user clears this bit or a hardware reset occurs.
7 RST3 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if STP = 0.
18.2.3 Timer Mode Registers (TMR1–TMR4)
The four timer mode registers (TMR1–TMR4) are shown in Figure 18-5.
Erratic behavior may occur if TGCR1 and TGCR2 are not initialized before the TMRs.
Only TGCR[RST] can be modified at any time.
0
Field
Reset
R/W
Addr 0x10D90 (TMR1); 0x10D92 (TMR2); 0x10DA0 (TMR3); 0x10DA2 (TMR4)
Figure 18-5. Timer Mode Registers (TMR1–TMR4)
18-6
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Description
7 8 9 10 11
CE OM ORI
R/W
12 13 14 15
FRR ICLK GE
MOTOROLA