Motorola PowerQUICC II MPC8280 Series Reference Manual page 1352

FCC Status Register (FCCS)
Figure 37-8 shows interrupts that can be generated in the HDLC protocol.
Frame
Received by HDLC
Time
RXD Line Idle
CD
HDLC FCCE
CD
Events
Notes:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the parallel I/O port, not in the FCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte
Frame
Transmitted by HDLC
TXD
RTS
CTS
HDLC FCCE
Events
Notes:
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CT event must be programmed in the parallel I/O port, not in the FCC itself.
37.10 FCC Status Register (FCCS)
The FCCS register, shown in Figure 37-9, allows the user to monitor real-time status
conditions on the RXD line. The real-time status of the CTS and CD signals are part of the
parallel I/O port; see Chapter 41, "Parallel I/O Ports."
37-16
Freescale Semiconductor, Inc.
Stored in Rx Buffer
F F A A C I
IDL FLG FLG
Stored in Tx Buffer
Line Idle F F
CT
Figure 37-8. HDLC Interrupt Event Example
MPC8280 PowerQUICC II Family Reference Manual
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I I CR CR F
RXB RXF FLG IDL
FLG
A A C CR CR F
TXB
Line Idle
CD
Line Idle
CT
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