Motorola PowerQUICC II MPC8280 Series Reference Manual page 958

Channel-Specific Parameters
Table 29-10. Channel-Specific Parameters for SS7
1 2
Offset Name Width
0x00 TSTATE Word
0x04 ZISTATE Word
0x08 ZIDATA0 Word
0x0C ZIDATA1 Word
0x10 TBDFlags Hword
0x12 TBDCNT Hword
0x14 TBDPTR Word
0x18 ECHAMR Word
0x1C TCRC Word
0x20 RSTATE Word
0x24 ZDSTATE Word
0x28 ZDDATA0 Word
0x2C ZDDATA1 Word
0x30 RBDFlags Hword
0x32 RBDCNT Hword
0x34 RBDPTR Word
0x38 MFLR Hword
29-20
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Tx internal state. The user must write to TSTATE 0xHH80_0000. HH is the TSTATE
High Byte. Refer to Section 29.3.1.1, "Internal Transmitter State (TSTATE)—HDLC
Mode."
Zero-insertion machine state. User-initialized to one of the following values:
0x10000207 for regular channel transmitting all 1s before first frame of data
0x00000207 for regular channel transmitting flags before first frame of data
0x30000207 for inverted channel transmitting all 1s before first frame of data
0x20000207 for inverted channel transmitting flags before first frame of data
Note: Used in conjunction with ZIDATA0 and ZIDATA1.
Zero-insertion high word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA1.
Zero-insertion low word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA0.
TxBD flags, used by the CP (read-only for the user)
Tx internal byte count. Number of remaining bytes in buffer, used by the CP
(read-only for the user)
Tx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
Extended channel mode register. See 29.3.4.1, "Extended Channel Mode Register
(ECHAMR)—SS7 Mode."
Temporary transmit CRC. Temporary value of CRC calculation result, used by the CP
(read-only for the user)
Rx internal state. To start a receiver channel the user must write to RSTATE
0xHH80_0000. HH is the RSTATE High Byte. Refer to Section 29.3.1.4, "Internal
Receiver State (RSTATE)—HDLC Mode."
Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel,
and 0x20FFFFE0 for reversed bit order channel)
Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
RxBD flags, used by the CP (read-only for the user)
Rx internal byte count. Number of remaining bytes in buffer, used by the CP
(read-only for the user)
Rx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
Maximum frame length register. Defines the longest expected frame for this channel.
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is
discarded and the LG flag is set in the last frame's BD. An interrupt request might be
generated (RXF and RXB) depending on the interrupt mask. A frame's length is
considered to be everything between flags, including CRC. No more data is written
into the current buffer when the MFLR violation is detected.
MPC8280 PowerQUICC II Family Reference Manual
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