Motorola PowerQUICC II MPC8280 Series Reference Manual page 476

SDRAM Machine
As seen in Table 11-19, the MPC8280 provides the following SDRAM interface
commands:
Command
Bank-activate Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM
sense amplifiers and must be restored with a
is issued.
Mode-set Allows setting of SDRAM options—CAS latency, burst type, and burst length. CAS latency depends
on the SDRAM device used (some SDRAMs provide CAS latency of 1, 2, or 3; some provide a
latency of 1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap
(sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, MPC8280
supports only a 4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size. MPC8280
does not support burst lengths of 1, 2, and a page for SDRAMs. The mode register data (CAS
latency, burst length, and burst type) is programmed into the P/LSDMR register by initialization
software at reset. After the P/LSDMR is set, the MPC8280 transfers the information to the SDRAM
array by issuing a
gives timing information.
Precharge Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers
(single bank/all to prepare for reading another row in the SDRAM array. A
banks) a read or write if the row address changes on the next access. Note that the MPC8280 uses the
SDA10 pin to distinguish the
with this format.
Read Latches the column address and transfers data from the selected sense amplifier to the output buffer
as determined by the column address. During each successive clock, additional data is output
without additional
At the end of the burst, the page remains open.
Refresh Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row
address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.
After being read, a row is automatically rewritten into the memory array. Both banks must be in a
precharged state before executing
Write Latches the column address and transfers data from the data signals to the selected sense amplifier
as determined by the column address. During each successive clock, additional data is transferred
to the sense amplifiers from the data signals without additional
data transferred is determined by the burst size. At the end of the burst, the page remains open.
11.4.4 Page-Mode Support and Pipeline Accesses
The SDRAM interface supports back-to-back page mode. A page remains open as long as
back-to-back accesses that hit the page are generated on the bus. The page is closed once
the bus becomes idle unless ORx[PMSEL] is set.
The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM
accesses and with one bubble for core accesses, as required by the 60x bus specification.
If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data phases
to occur with zero clocks of separation for CPM accesses and with one clock of separation
for core accesses, as required by the 60x bus specification.
11-38
Freescale Semiconductor, Inc.
Table 11-19. SDRAM Interface Commands
- command. Section 11.4.9, "SDRAM Mode-Set Command Timing,"
MODE SET
PRECHARGE
commands. The amount of data transferred is determined by the burst size.
READ
REFRESH
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Description
command before another
PRECHARGE
command must be issued after
PRECHARGE
- - command. The SDRAMs must be compatible
ALL BANKS
.
WRITE
-
BANK ACTIVATE
commands. The amount of
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