Motorola PowerQUICC II MPC8280 Series Reference Manual page 1392

2
The I C Buffer Descriptor (BD) Table
Table 40-9 describes I
Table 40-9. I
Bits Name
0 E Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1 — Reserved and should be cleared.
2 W Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is full.
1 The I2CER[RXB] is set when the CP fills this buffer, indicating that the core needs to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
4 L Last. The I
0 This buffer does not contain the last character of the message.
1 This buffer holds the last character of the message. The I
data is placed into the associated buffer, or because of a stop or start condition or an overrun.
5–13 — Reserved and should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception. The I
after the received data is placed into the associated buffer.
15 — Reserved and should be cleared.
40.7.1.2 I C Transmit Buffer Descriptor (TxBD)
2
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The first word
of the TxBD, shown in Figure 40-14, contains status and control bits.
0 1 2
Offset + 0 R — W
Offset + 2
Offset + 4
Offset + 6
40-14
Freescale Semiconductor, Inc.
2
C RxBD status and control bits.
2
C RxBD Status and Control Bits
2
C controller sets L.
3 4 5 6
I L S
Tx Buffer Pointer
Figure 40-14. I
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
2
C controller sets L after all received
—
Data Length
2
C TxBD
2
C controller updates this bit
12 13 14 15
NAK UN CL
MOTOROLA