Motorola PowerQUICC II MPC8280 Series Reference Manual page 724

SCC Buffer Descriptors (BDs)
error condition is reported—an underrun error when sending and a busy error when
receiving. Figure 20-7 shows the SCC BD table and buffer structure.
Dual-Port RAM
SCCx TxBD
Table
SCCx RxBD
Table
SCCx RxBD
Table Pointer
SCCx TxBD
Table Pointer
Figure 20-7. SCC BD and Buffer Memory Structure
In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because
dual-port RAM is used for descriptors, buffers are usually put in external RAM, especially
if they are large.
The CPM processes TxBDs straightforwardly; when the transmit side of an SCC is enabled,
the CPM starts with the first BD in that SCC TxBD table. Once the CPM detects that the R
bit is set in the TxBD, it starts processing the buffer. The CPM detects that the BD is ready
when it polls the R bit or when the user writes to the TODR. After data from the BD is put
in the Tx FIFO, if necessary the CPM waits for the next descriptor's R bit to be set before
proceeding. Thus, the CPM does no look-ahead descriptor processing and does not skip
BDs that are not ready. When the CPM sees a BD's W bit (wrap) set, it returns to the start
of the BD table after this last BD of the table is processed. The CPM clears R (not ready)
after using a TxBD, which keeps it from being retransmitted before it is confirmed by the
core. However, some protocols support a continuous mode (CM), for which R is not cleared
(always ready).
The CPM uses RxBDs similarly. When data arrives, the CPM performs required processing
on the data and moves resultant data to the buffer pointed to by the first BD; it continues
until the buffer is full or an event, such as an error or end-of-frame detection, occurs. The
20-12
Freescale Semiconductor, Inc.
Status and Control
Buffer Length
Buffer Pointer
Status and Control
Buffer Length
Buffer Pointer
MPC8280 PowerQUICC II Family Reference Manual
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Tx Buffer Descriptors
Rx Buffer Descriptors
External Memory
Tx Buffer
Rx Buffer
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