Motorola PowerQUICC II MPC8280 Series Reference Manual page 1032

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VCI/VPI Address Lookup Mechanism
Table 31-3. Field Descriptions for Address Compression (continued)
Field
Ch Code Pointer to internal or external connection table.
Reserved, should be cleared.
MS
Match status.
0 Match was found.
1 Match was not found.
31.4.2.1 VP-Level Address Compression Table (VPLT)
The size of the VP-level table depends on the number of mask bits in VP_MASK. For
example, if only one PHY is available (PHY address = 0) and VPMASK =
0b11_1111_1111, VP pointer contains ten bits and the table is 4 Kbytes. Because each
VPLT entry is 4 bytes, the address of an entry is VPT_BASE + VP pointer × 4.
Each VPLT entry has two parameters:
• VC_MASK—A 16-bit VC-level mask for masking the incoming cell's VCI
• VCOFFSET—A 16-bit VC-level table offset from VC_BASE that points to the
appropriate VC-level table's (VCLT) starting address. The address of the VCLT is
VC_BASE + VCOFFSET × 4.
If the VCLTs are to be placed contiguously in memory, each table's VCOFFSET
depends on the size of preceding tables. Each table's size depends on the number of
ones in VC_MASK. Figure 31-6 gives the general formula for determining
VCOFFSET.
General formula: VCOFFSET
Figure 31-6. General VCOFFSET Formula for Contiguous VCLTs
Table 31-4 shows example VCOFFSET calculations for a VP-level table with four
entries.
Table 31-4. VCOFFSET Calculation Examples for Contiguous VCLTs
VP-Level Table
Entry
0
1
2
3
The MPC8280 can check that all unallocated bits of the PHY + VPI are 0 by setting
GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell
is considered a misinserted cell.
31-18
Freescale Semiconductor, Inc.
= VCOFFSET
(n+1)
Number of Ones in
VC_MASK
VC_MASK
0x0237
6
0x0230
3
0xA007
5
x
x
MPC8280 PowerQUICC II Family Reference Manual
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Description
(number of ones in VC_MASKn)
+ 2
n
VC-Level
Table Size
6
2
= 64 entries
3
2
= 8 entries
5
2
= 32 entries
x
VCOFFSET
0
64
64 + 8 = 72
72 + 32 = 104
MOTOROLA

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