Motorola PowerQUICC II MPC8280 Series Reference Manual page 494

General-Purpose Chip-Select Machine (GPCM)
In this section, the output-enable and write-enable signals are generically labeled OE and
WE. When using the 60x bus they refer to POE and PWE, and for the local bus they refer
to LOE and LWE.
Figure 11-40 shows a simple connection between a 32-bit port size SRAM device and the
MPC8280.
Figure 11-40. GPCM-to-SRAM Configuration
11.5.1 Timing Configuration
If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx.
These attributes include the CSNT, ACS[0–1], SCY[0–3], TRLX, EHTR, and SETA fields.
Table 11-31 shows signal behavior and system response.
Option Register Attributes
TRLX Access ACS CSNT
0 Read 00
0 Read 10
0 Read 11
0 Write 00
0 Write 10
0 Write 11
0 Write 00
0 Write 10
0 Write 11
1 Read 00
1 Read 10
1 Read 11
1 Write 00
1 Write 10
11-56
Freescale Semiconductor, Inc.
MPC8280
CSx
WE[0–3]
GPL_x1/OE
A[15–29]
D[0–31]
Table 11-31. GPCM Strobe Signal Behavior
Address to CS CS Negated to
Asserted Address Change
x 0
x 1/4*Clock
x 1/2*Clock
0 0
0 1/4*Clock
0 1/2*Clock
1 0
1 1/4*Clock
1 1/2*Clock
x 0
x (1+1/4)*Clock
x (1+1/2)*Clock
0 0
0 (1+1/4)*Clock
MPC8280 PowerQUICC II Family Reference Manual
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32-Bit Wide SRAM
CE 128K
WE[0–3]
OE
Address
Data
Signal Behavior
WE Negated to
Address/Data Invalid
0
0
0
0
0
0
0 -1/4*Clock
-1/4*Clock -1/4*Clock
-1/4*Clock -1/4*Clock
0
0
0
0
0
Total Cycles
1
x 2+SCY
x 2+SCY
x 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
2+SCY
2+SCY
2+SCY
x 2+2*SCY
x 3+2*SCY
x 3+2*SCY
0 2+2*SCY
0 3+2*SCY
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