Motorola PowerQUICC II MPC8280 Series Reference Manual page 915

sequence is sent, data from two ready transmit buffers can be sent on the transmit signal
with no delay between them.
28.3.8 Handling Errors in the SMC UART Controller
The SMC UART controller reports character reception error conditions via the channel
BDs and the SMCE. Table 28-6 describes the reception errors. The SMC UART controller
has no transmission errors.
Error
Overrun The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the
first character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the
received character into the internal FIFO. It then writes the character to the buffer, closes it, sets the OV
bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Overrun errors that occasionally occur when the line is idle can be ignored.
Parity The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and
generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Idle An idle is found when a character of all ones is received, at which point the channel counts consecutive
Sequence idle characters. If the count reaches MAX_IDL, the buffer is closed and an RXB interrupt is generated.
Receive If no receive buffer is open, this does not generate an interrupt or any status information. The idle counter
is reset each time a character is received.
Framing The SMC received a character with no stop bit. When it occurs, the channel writes the received
character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is
enabled. When this error occurs, parity is not checked for the character.
Break The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,
Sequence generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is
closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled.
28.3.9 SMC UART RxBD
Using the BDs, the CP reports information about the received data on a per-buffer basis.
Then it closes the current buffer, generates a maskable interrupt, and starts receiving data
into the next buffer after one of the following occurs:
• An error is received during message processing
• A full receive buffer is detected
• A programmable number of consecutive idle characters are received
MOTOROLA
Freescale Semiconductor, Inc.
Table 28-6. SMC UART Errors
Chapter 28. Serial Management Controllers (SMCs)
For More Information On This Product,
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Description
SMC in UART Mode
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