Motorola PowerQUICC II MPC8280 Series Reference Manual page 1253

Table 34-19. IMA Link Receive Table Entry
Offset Name
0x08 DCBSP
0x0A DCBEP
0x0C DCBFP
0x0E DCBRP
0x10 RICPCH
0x12 IRINTMSK
0x13 LICPOS
0x14 IRSEC
0x18 ANOMALY_CTR
0x19 ALPHABETA_CTR
0x1A GAMMA_CTR
0x1C DEFECT_CTR
1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
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Width
Hword IMA link delay compensation buffer start pointer. This parameter forms
bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits
28-31 are zero. Refer to Section 34.4.6.2, "Delay Compensation
Buffers (DCB) for more details.
Hword IMA link delay compensation buffer end pointer. This parameter forms
bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits
28-31 are zero. Refer to Section 34.4.6.2, "Delay Compensation
Buffers (DCB) for more details.
Hword IMA link delay compensation buffer fill pointer. Microcode-managed
parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are
from IMAEXTBASE, and bits 28-31 are zero.
Initialize to DCBSP at link startup.
Hword IMA link delay compensation buffer read pointer. Only used during
group delay synchronization and link addition. Microcode-managed
parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are
from IMAEXTBASE, and bits 28-31 are zero.
Hword Receive ICP channel number. ATM receive channel number to which
received ICP cells are sent.
Byte IMA receive interrupt mask. Has the same format as the IMA interrupt
queue entry.; however, only receive-related bits are relevant. Setting a
bit enables the associated interrupt; clearing a bit masks it.
For group-related events, only the mask register for the TRL is
referenced.
Byte Link ICP offset. Program to the ICP offset validated for this link.
Word IMA receive stuff event counter. Increments each time a stuff event is
received on this ink. Initialize to zero at link startup.
Byte Anomaly counter. Microcode-managed parameter. Initialize to zero at
link startup.
Byte Alpha/beta counter. Microcode-managed parameter. Initialize to zero at
link startup.
Byte Gamma counter. Microcode-managed parameter. Initialize to zero at
link startup.
Word Defect counter. This counter is active while the link is in the
Loss-of-IMA-Frame (LIF) state and is used to ensure IFSD interrupts
are generated for every GAMMA+2 frames. Software can use the
period interrupt issued by this counter in order to determine if the link
is taking too long to synchronize. The DEFECT_CTR is active before
IFSM reaches SYNC. It starts counting from the first cell received and
will count from 0 to (GAMMA+2) x M. When it reaches (GAMMA+2) x M
an IFSD interrupt is generated and the counter is reset. Upon reception
of the next cell it starts to count again and subsequent interrupts are
generated. Microcode managed parameter. Initialize to zero at link
startup.
Chapter 34. Inverse Multiplexing for ATM (IMA)
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IMA Programming Model
1
(continued)
Description
34-43