Motorola PowerQUICC II MPC8280 Series Reference Manual page 671

Table 18-1. TGCR1 Field Descriptions (continued)
Bits Name
2 STP 2 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
3 RST2 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
4 GM1 Gate mode for TGATE1. This bit is valid only if the gate function is enabled in TMR1 or TMR2.
0 Restart gate mode. TGATE1 is used to enable/disable count. A falling TGATE1 enables and
restarts the count and a rising edge of TGATE1 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not
restart the count value in TCN.
5 — Reserved, should be cleared.
6 STP1 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
7 RST1 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if STP = 0.
The TGCR2 register is shown in Figure 18-4.
0
Field CAS4
Reset
R/W
Addr
Figure 18-4. Timer Global Configuration Register 2 (TGCR2)
Table 18-2 describes TGCR2 fields.
Bit Name
0 CAS4 Cascade timers.
0 Normal operation.
1 Timers 3 and 4 cascades to form a 32-bit timer.
1 — Reserved, should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
1 2 3
— STP4 RST4
Table 18-2. TGCR2 Field Descriptions
Chapter 18. Timers
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General-Purpose Timer Units
Description
4 5
GM2 —
0000_0000
R/W
0x10D84
Description
6 7
STP3 RST3
18-5