Motorola PowerQUICC II MPC8280 Series Reference Manual page 1062

ATM Memory Structure
Offset Bits Name
0x00 0–1 —
2 GBL
3–4 BO
5 —
6 DTB
7 BIB
8 —
9 BUFM
10 SEGF
11 ENDF
12–13 —
14–15 INTQ
31-48
Freescale Semiconductor, Inc.
Table 31-16. RCT Field Descriptions
Reserved, should be cleared.
Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free
buffer pool.
Byte ordering—used for data buffers.
00 Reserved
01 Munged little endian
1x Big endian
Reserved, should be cleared.
Data buffers bus
0 Data buffers reside on the 60x bus.
1 Data buffers reside on the local bus.
BD, interrupt queues, free buffer pool and external SRTS logic bus
0 Reside on the 60x bus.
1 Reside on the local bus.
Note that when using AAL5 or AAL1 CES in UDC mode, BDs must be placed on the
same bus (RCT[DTB] = RCT[BIB]). This is necessary because in UDC mode the
user-defined header, which is part of the cell data, is read using the same bus
configuration (byte ordering and bus type) as the payload. Therefore, if data is placed
on the 60x bus and the BD on the local bus, the SDMA accesses the UDC header on
the 60x bus with the address of the local bus.
Reserved, should be cleared.
Buffer mode. (AAL5 only) See Section 31.10.5.3, "ATM Controller Buffers."
0 Static buffer allocation mode. Each BD is associated with a dedicated buffer.
1 Global buffer allocation mode. Free buffers are fetched from global free buffer pools.
OAM F5 segment filtering
0 Do not send cells with PTI = 100 to the raw cell queue.
1 Send cells with PTI = 100 to the raw cell queue.
OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
Reserved, should be cleared.
Points to one of four interrupt queues available.
MPC8280 PowerQUICC II Family Reference Manual
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