Motorola PowerQUICC II MPC8280 Series Reference Manual page 1370

SPI Parameter RAM
39.5 SPI Parameter RAM
The SPI parameter RAM area is similar to the SCC general-purpose parameter RAM. The
CP accesses the SPI parameter table using a user-programmed pointer (SPI_BASE) located
in the parameter RAM; see Section 14.5.2, "Parameter RAM." The SPI parameter table can
be placed at any 64-byte aligned address in the dual-port RAM's general-purpose area
(banks 1–8, 11 and 12). Some parameter values must be user-initialized before the SPI is
enabled; the CP initializes the others. Once initialized, parameter RAM values do not
usually need to be accessed. They should be changed only when the SPI is inactive.
Table 39-5 shows the memory map of the SPI parameter RAM.
Table 39-5. SPI Parameter RAM Memory Map
1
Offset Name Width
0x00 RBASE Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM.
0x02 TBASE Hword
0x04 RFCR Byte
0x05 TFCR Byte
0x06 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to define the maximum
0x08 RSTATE Word Rx internal state.
0x0C — Word The Rx internal data pointer
0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be
0x12 — Hword The Rx internal byte count
0x14 — Word Rx temp.
0x18 TSTATE Word Tx internal state.
39-12
Freescale Semiconductor, Inc.
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling
the SPI. Furthermore, do not configure BD tables of the SPI to overlap any other active
controller's parameter RAM.
RBASE and TBASE should be divisible by eight.
Rx/Tx function code registers. The function code registers contain the transaction
specification associated with SDMA channel accesses to external memory. See
Section 39.5.1, "Receive/Transmit Function Code Registers (RFCR/TFCR)."
number of bytes the MPC8280 writes to a Rx buffer before moving to the next buffer. The
MPC8280 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but
never exceeds the MRBLR value. User-supplied buffers should be no smaller than
MRBLR.
Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes
to be sent is programmed in TxBD[Data Length].
MRBLR is not intended to be changed while the SPI is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next RxBD. To
guarantee the exact RxBD on which the change occurs, change MRBLR only while the
SPI receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
Reserved for CP use.
in the buffer to be accessed.
serviced when idle. After a reset or when the end of the BD table is reached, the CP
initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but
it can be updated when the receiver is disabled or when no Rx buffer is in use.
2
and decremented with every byte the SDMA channels write.
2
Reserved for CP use.
2
Reserved for CP use.
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Description
2
is updated by the SDMA channels to show the next address
is a down-count value that is initialized with the MRBLR value
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