Motorola PowerQUICC II MPC8280 Series Reference Manual page 1167

the MPC8280 uses the super-frame sync signal to know when to supply the signaling
information to the external framer. The external framer then places the signaling
information at the appropriate position in the super frame. See Section 32.4.6,
"Channel Associated Signaling (CAS) Support."
• Simple external logic is needed to synchronize the MCC-to-framer serial
connection. When going from TDM-to-ATM, the CAS information should be read
by the MCC on the 24th frame of a super frame.
• The adaptive rate FIFO method can be implemented by the core by calculating the
difference between the ATM and MCC pointers.
• When going from TDM-to-ATM, the ATM channel should be programmed to work
at a higher rate than the MCC super-channel rate. We expect that the jitter caused by
the APC traffic reshaping will depend on the ATM channel rate (PCR,
PCR_FRACTION). Figure 32-32 illustrates this timing issue. See also
Section 32.4.1.2, "TDM-to-ATM."
MCC timing:
BDs are ready to be transmitted at the rate shown below.
ATM timing:
The optimal ATM channel rate would match the MCC super channel rate exactly.
ATM timing (adjusted to higher rate):
If PCR and PCR_FACTION cannot provide the exact MCC super channel rate, the
ATM channel should be programmed to a higher rate to avoid the MCC buffer-not-ready
state. It is recommended that the ATM rate be double that of the MCC.
Extra request at the higher rate to compensate for jitter.
Note that some of the extra requests will not be needed (buffer-not-ready) and will
be ignored by the ATM controller.
MOTOROLA
Freescale Semiconductor, Inc.
Figure 32-32. TDM-to-ATM Timing Issue
Chapter 32. ATM AAL1 Circuit Emulation Service
For More Information On This Product,
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Application Considerations
32-47