Motorola PowerQUICC II MPC8280 Series Reference Manual page 1384

2
I C Registers
An MPC8280 I 2 C controller attempting a master read request could simultaneously be
targeted for an external master write (slave read). Both operations trigger the controller's
I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which
operation caused the interrupt, software must verify that its transmit operation actually
completed before assuming that the received data is the result of its read operation.
Problems could also arise if the MPC8280's I
and BD for a write request, but then is the target of a read request from another master.
Without software precautions, the I
transmit buffer originally intended for its own write request. To avoid this situation, a
higher-level handshake protocol must be used. For example, a master, before reading a
slave, writes the slave with a description of the requested data (which register should be
read, for example). This operation is typical with many I
In addition, it is not recommended to enable the MPC8280's I
2
I C master is executing transactions on the bus. The MPC8280's I
for the bus to become idle.
The MPC8280's I 2 C controller assumes that other I
to the I 2 C specification. Unexpected behavior can occur if the MPC8280 I
connected with devices which operate outside the specification. For example, a slave
device which acknowledges a master write with two SCL pulses instead of one (total of 10
SCL pulses), can cause wrong behavior of the PowerQUICC I
transaction.
40.4 I C Registers
2
The following sections describe the I
40.4.1 I C Mode Register (I2MOD)
2
2
The I C mode register, shown in Figure 40-6, controls the I
0
Field —
Reset
R/W
Addr
40-6
Freescale Semiconductor, Inc.
2 C controller responds to the other master with the
2
C registers.
1 2
REVD GCD
2
Figure 40-6. I C Mode Register (I2MOD)
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2 C controller master sets up a transmit buffer
2 C devices.
2 C controller while another
2
2 C devices on the bus closely conform
2
2 C modes and clock source.
3 4 5
FLT
0000_0000
R/W
0x11860
C controller should wait
2 C controller is
C controller on its next
6 7
PDIV EN
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