Motorola PowerQUICC II MPC8280 Series Reference Manual page 729

2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit
speed is fast or the interrupt delay is long, the SCC may have sent more than one Tx
buffer. Thus, it is important to check more than one TxBD during interrupt
handling. A common practice is to process all TxBDs in the handler until one is
found with its R bit set.
3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As
with transmit buffers, if the receive speed is fast or the interrupt delay is long, the
SCC may have received more than one buffer and the handler should check more
than one RxBD. A common practice is to process all RxBDs in the interrupt
handler until one is found with RxBD[E] set.
4. Execute the rfi instruction.
Additional information about interrupt handling can be found in Section 4.2, "Interrupt
Controller."
20.3.4 Initializing the SCCs
The SCCs require that a number of registers and parameters be configured after a power-on
reset. Regardless of the protocol used, follow these steps to initialize SCCs:
1. Write the parallel I/O ports to configure and connect the I/O pins to the SCCs.
2. Configure the parallel I/O registers to enable RTS, CTS, and CD if these signals are
required.
3. If the time-slot assigner (TSA) is used, the serial interface (SIx) must be
configured. If the SCC is used in NMSI mode, CMXSCR must still be initialized.
4. Write all GSMR bits except ENT or ENR.
5. Write the PSMR.
6. Write the DSR.
7. Initialize the required values for this SCC's parameter RAM.
8. Initialize the transmit/receive parameters via the CP command register (CPCR).
9. Clear out any current events in SCCE (optional).
10. Write ones to SCCM register to enable interrupts.
11. Set GSMR_L[ENT] and GSMR_L[ENR].
Descriptors can have their R or E bits set at any time. Notice that the CPCR does not need
to be accessed after a hardwarereset. An SCC should be disabled and reenabled after any
dynamic change to its parallel I/O ports or serial channel physical interface configuration.
A full reset can also be implemented using CPCR[RST].
MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
Freescale Semiconductor, Inc.
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SCC Parameter RAM
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