Motorola PowerQUICC II MPC8280 Series Reference Manual page 824

SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions
Bit Name
6 CM Continuous mode.
0 Normal operation.
1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent
when the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during
transmission, regardless of how CM is set.
7–13 — Reserved, should be cleared.
14 UN Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer.
15 CT CTS lost. Indicates the CTS was lost during frame transmission.
Data length and buffer pointer fields are described in Section 20.2, "SCC Buffer
Descriptors (BDs)." Although it is never modified by the CP, data length should be greater
than zero. The buffer pointer can be even or odd and can reside in internal or external
memory.
24.12 SCC Transparent Event Register (SCCE)/Mask
Register (SCCM)
When the SCC is in transparent mode, the SCC event register (SCCE) functions as the
transparent event register to report events recognized by the transparent channel and to
generate interrupts. When an event is recognized, the transparent controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the
equivalent bits in the transparent mask register (SCCM).
Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be
reset before the CP clears the internal interrupt request to the SIU interrupt controller.
Figure 24-4 shows the event and mask registers.
0 1 2
Field —
Reset
R/W
Addr 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)
Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
24-12
Freescale Semiconductor, Inc.
3 4 5 6
DCC —
0000_0000_0000_0000
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Description
7 8 9 10 11
GRA — TXE
R/W
12 13 14 15
— BSY TXB RXB
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