Motorola PowerQUICC II MPC8280 Series Reference Manual page 715

• Clocks can be derived from a baud rate generator, an external pin, or DPLL
• Data rate for asynchronous communication can be as high as 16.62 Mbps at
133 MHz
• Supports automatic control of the RTS, CTS, and CD modem signals
• Multi-buffer data structure for receive and send (the number of buffer descriptors
(BDs) is limited only by the size of the internal dual-port RAM—8 bytes per BD)
• Deep FIFOs (SCC transmit and receive FIFOs are 32 bytes each.)
• Transmit-on-demand feature decreases time to frame transmission (transmit
latency)
• Low FIFO latency option for send and receive in character-oriented and totally
transparent protocols
• Frame preamble options
• Full-duplex operation
• Fully transparent option for one half of an SCC (Rx/Tx) while another protocol
executes on the other half (Tx/Rx)
• Echo and local loopback modes for testing
20.1.1 The General SCC Mode Registers (GSMR1–GSMR4)
Each SCC contains a general SCC mode register (GSMR) that defines options common to
most of the protocols. GSMR_L contains the low-order 32 bits; GSMR_H, shown in
Figure 20-2, contains the high-order 32 bits. Some GSMR operations are described in later
sections.
0
Field
Reset
R/W
Addr 0x11A04 (GSMR1); 0x11A24 (GSMR2); 0x11A44 (GSMR3); 0x11A64 (GSMR4)
16 17 18
Field TCRC REVD TRX TTX CDP CTSP CDS CTSS
Reset
R/W
Addr 0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4)
Figure 20-2. GSMR_H—General SCC Mode Register (High Order)
MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
Freescale Semiconductor, Inc.
0000_0000_0000_0000
19 20 21 22
0000_0000_0000_0000
For More Information On This Product,
Go to: www.freescale.com
—
R/W
23 24 25 26
TFL RFW TXSY
R/W
Features
14 15
27 28 29 30 31
SYNL RTSM RSYN
20-3