Motorola PowerQUICC II MPC8280 Series Reference Manual page 1129

Figure 32-6 shows the flow of TDM-to-ATM interworking.
UTOPIA
interface
TDM
interface
32.4.2 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized; that
is, that they are using a synchronized serial clock. If the TDM interfaces are not
synchronized, a slip can occur in the reassembly buffer. In order to prevent the overrun and
underrun condition, the MPC8280 maintains an adaptive slip control using a set of 4
threshold pointers and a counter for each ATM-TDM (VC to super channel) connection.
Before a buffer-not-ready event (ATM-to-TDM data forwarding) occurs at the MCC
transmitter, the MCC buffer pointer reaches the MCC_Stop threshold. Consequently, the
MCC pointer freezes on the last transmitted BD and starts sending the underrun template
(or the last transmitted frame). In the meantime, the ATM receiver continues to write valid
data and advance the ATM buffer pointer. When the adaptive counter CESAC reaches the
MCC_start threshold and the MCC has finished sending a multiple frame size, the MCC
exits the pre-underrun state, starts sending the valid received data and advances the MCC
buffer pointer. (Refer to Section 32.5, "ATM-to-TDM Adaptive Slip Control.")
The same mechanism is implemented on the ATM side. When the ATM receiver
(ATM-to-TDM data forwarding) reaches the ATM_Stop threshold (pre-overrun), the ATM
controller switches to hunt mode and discards the channel's incoming cells. In the
meantime, the MCC transmitter continues to send valid data and advance the MCC buffer
pointer. When CESAC falls to the ATM_start threshold, the ATM write pointer is advanced
to the first BD after the one marked with EOSF (in CAS mode). When this BD is ready and
CESAC reaches the ATM_Start threshold, the receiver's write pointer is not longer in
danger of overrunning the read pointer of the MCC transmitter; that is, it is safe to begin
receiving cells again. The ATM receiver then begins the resynchronization process: for
unstructured AAL1 type the ATM receiver waits for the first valid cell, and for structured
AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first
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Freescale Semiconductor, Inc.
ATM
ATM
Tx pointer
Tx
MCC
MCC
Rx pointer
Rx
Note: The MCC Rx should be programmed to operate in
opposite polarity E (Empty) bit.
Figure 32-6. TDM-to-ATM Interworking
Chapter 32. ATM AAL1 Circuit Emulation Service
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Interworking Functions
BD table
0 BD 1
1 BD 2
1 BD 3
0 BD 4
0 BD 5
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
32-9