Motorola PowerQUICC II MPC8280 Series Reference Manual page 1063

Table 31-16. RCT Field Descriptions (continued)
Offset Bits Name
0x02 0 —
1 INF
2–11 —
12 ABRF
13–15 AAL
0x04 — RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer.
0x08 — Cell Time
Stamp
0x0C — RBD_Offset RxBD offset from RBD_BASE. Points to the channel's current BD. User-initialized to
0x0E-0x —
18
0x1A — MRBLR
0x1C 0–1 —
2–7 PMT
8–15 RBD_BASE RxBD base. Points to the first BD in the channel's RxBD table. The 8 most-significant
0x1E 0–11
12–14 —
15 PM
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
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Internal use only. Should be cleared.
(AAL5 only) Indicates the receiver state. Initialize to 0
0 In idle state.
1 In AAL5 frame reception state.
Internal use only. Should be cleared.
(AAL5 only). Controls ABR flow.
0 ABR flow control is disabled.
1 ABR flow control is enabled.
AAL type
000 AAL0—Reassembly with no adaptation layer
001 AAL1—ATM adaptation layer 1 protocol
010 AAL5—ATM adaptation layer 5 protocol
100 AAL2—ATM adaptation layer 2 protocol. Refer to Chapter 33, "ATM AAL2."
101 AAL1_CES—Refer to Chapter 32, "ATM AAL1 Circuit Emulation Service."
All others reserved.
Used for reassembly time-out. Whenever a cell is received, the MPC8280 time stamp
timer is sampled and written to this field. See Section 14.3.8, "RISC Time-Stamp
Control Register (RTSCR)."
0; updated by the CP.
Protocol-specific area.
Maximum receive buffer length. Used in both static and dynamic buffer allocation.
Reserved, should be cleared.
Performance monitoring table. Points to one of the available 64 performance
monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be
changed on-the-fly.
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four
least-significant bits of the address are taken as zeros.
Reserved, should be cleared.
Performance monitoring. Can be changed on-the-fly.
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received for this VC
the performance monitoring table that its code is written in the PMT field is updated.
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ATM Memory Structure
Description
31-49