Motorola PowerQUICC II MPC8280 Series Reference Manual page 700

IDMA Operation
Table 19-7. Valid Memory-to-Memory STS/DTS Values (continued)
Internal
DMA_WRAP Buffer SS_MAX
Size
101 2048 63 * 32
Table 19-8 describes valid STS/DTS values for memory/peripheral operations.
Table 19-8. Valid STS/DTS Values for Peripherals
DMA_WRAP Internal Buffer Size SS_MAX
000 64
001 128
010 256
011 512
100 1024
101 2048
1
These values come out as a single transaction on the bus.
2
Peripherals that can accept bursts of 32 bytes are supported.
19.8.3 IDMA Performance
The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of
data transferred for each
19-24
Freescale Semiconductor, Inc.
STS (in Bytes)
63 * 32
63 * 32, 9 * 32, 7 * 32, 32
S/D Mode
1 * 32 01
10
3 * 32 01
10
7 * 32 01
10
15 * 32 01
10
31 * 32 01
10
63 * 32 01
10
_ command issued. Using large internal IDMA
START IDMA
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Number of Transfers to Fill
DTS (in Bytes)
63 * 32, 9 * 32, 7 * 32, 32
63 * 32 1, 7, 9, 63
STS (in Bytes)
1 * 32
1, 2, 4, 8 (single); 32
(burst)
3 * 32
1, 2, 4, 8 (single); 32
(burst)
7 * 32
1, 2, 4, 8 (single); 32
(burst)
15 * 32
1, 2, 4, 8 (single); 32
(burst)
31 * 32
1, 2, 4, 8 (single); 32
(burst)
63 * 32
1, 2, 4, 8 (single); 32
(burst)
Internal Buffer
STS Size DTS Size
1 1, 7, 9, 63
1
DTS (in Bytes)
1
1, 2, 4, 8 (single) ; 32
2
(burst)
1 * 32
1, 2, 4, 8 (single); 32
(burst)
3 * 32
1, 2, 4, 8 (single); 32
(burst)
7 * 32
1, 2, 4, 8 (single); 32
(burst)
15 * 32
1, 2, 4, 8 (single); 32
(burst)
31 * 32
1, 2, 4, 8 (single); 32
(burst)
63 * 32
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