Motorola PowerQUICC II MPC8280 Series Reference Manual page 725

buffer is then closed; subsequent data uses the next BD. If E = 0, the current buffer is not
empty and it reports a busy error. The CPM does not move from the current BD until E is
set by the core (the buffer is empty). After using a descriptor, the CPM clears E (not empty)
and does not reuse a BD until it has been processed by the core. However, in continuous
mode (CM), E remains set. When the CPM discovers a descriptor's W bit set (indicating it
is the last BD in the circular BD table), it returns to the beginning of the table when it is
time to move to the next buffer.
20.3 SCC Parameter RAM
Each SCC parameter RAM area begins at the same offset from each SCC base area.
Section 20.3.1, "SCC Base Addresses," describes the SCC's base addresses. The
protocol-specific portions of the SCC parameter RAM are discussed in the specific protocol
descriptions and the part that is common to all SCC protocols is shown in Table 20-4.
Some parameter RAM values must be initialized before the SCC can be enabled. Other
values are initialized or written by the CPM. Once initialized, most parameter RAM values
do not need to be accessed because most activity centers around the descriptors rather than
the parameter RAM. However, if the parameter RAM is accessed, note the following:
• Parameter RAM can be read at any time.
• Tx parameter RAM can be written only when the transmitter is disabled—after a
STOP TRANSMIT
buffer/frame finishes transmitting after a
before a
RESTART TRANSMIT
• Rx parameter RAM can be written only when the receiver is disabled. Note the
command does not stop reception, but it does allow the user to extract
CLOSE RXBD
data from a partially full Rx buffer.
• See Section 20.3.7, "Reconfiguring the SCCs."
Table 20-4 shows the parameter RAM map for all SCC protocols. Boldfaced entries must
be initialized by the user.
Table 20-4. SCC Parameter RAM Map for All Protocols
1
Offset Name Width
0x00 RBASE Hword Rx/TxBD table base address—offset from the beginning of dual-port RAM. The BD
0x02 TBASE Hword
0x04 RFCR Byte
0x05 TFCR Byte
MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
Freescale Semiconductor, Inc.
command and before a
command.
tables can be placed in any unused portion of the dual-port RAM. The CPM starts BD
processing at the top of the table. (The user defines the end of the BD table by setting
the W bit in the last BD to be processed.) Initialize these entries before enabling the
corresponding channel. Erratic operations occur if BD tables of active SCCs overlap.
Values in RBASE and TBASE should be multiples of eight.
Rx function code. See Section 20.3.2, "Function Code Registers (RFCR and TFCR)."
Tx function code. See Section 20.3.2, "Function Code Registers (RFCR and TFCR)."
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command or after the
RESTART TRANSMIT
GRACEFUL STOP TRANSMIT
Description
SCC Parameter RAM
command and
20-13