Motorola PowerQUICC II MPC8280 Series Reference Manual page 480

SDRAM Machine
CLK
ALE
CS
SDRAS
SDCAS
MA11
MA10
MA[0–9]
WE
DQM
PRETOACT = 2
PRECHARGE
Command
Bank A
Figure 11-20. PRETOACT = 2 (2 Clock Cycles)
11.4.6.2 Activate to Read/Write Interval
As represented in Figure 11-21, this parameter, controlled by P/LSDMR[ACTTORW],
defines the earliest timing for
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Rbz
WE
DQM
DATA
ACTTORW = 2
ACTIVATE
Command
Figure 11-21. ACTTORW = 2 (2 Clock Cycles)
11-42
Freescale Semiconductor, Inc.
RAy
RAy
ACTIVATE
Command
Bank A
/ command after an
READ WRITE
Cbz
D0 D1 D2
WRITE
Command
MPC8280 PowerQUICC II Family Reference Manual
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ACTIVATE
D3
command.
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