Boundary Scan Register
the input pins, forcing fixed values on the output signal pins, and selecting the direction and
drive characteristics (a logic value or high impedance) of the bidirectional and three-state
signal pins. Figure 13-3, Figure 13-4, Figure 13-5, and Figure 13-6 show various cell types.
1 — EXTEST | Clamp
0 — Otherwise
G1
Data from
System
1
Logic
1
Data to
System
Logic
Figure 13-4. Observe-Only Input Pin Cell (I.Obs)
13-4
Freescale Semiconductor, Inc.
Shift DR
MUX
G1
1
1
From Last Cell
Figure 13-3. Output Pin Cell (O.Pin)
To Next Cell
D
C
Clock DR
MPC8280 PowerQUICC II Family Reference Manual
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To Next Cell
D
MUX
C
Clock DR
Update DR
G1
1
MUX
1
Shift DR
From Last Cell
To Output
Buffer
D
C
Input
Pin
MOTOROLA