Motorola PowerQUICC II MPC8280 Series Reference Manual page 529

CLKIN
A
Row
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
cst1 0
cst2 0
cst3 0
cst4 0
bst1 1
bst2 1
bst3 1
bst4 1
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop 0
exen 0
amx0 1
amx1 0
na 0
uta 0
todt 0
last 0
RBS
Figure 11-71. Burst Read Access to FPM DRAM (LOOP)
MOTOROLA
Freescale Semiconductor, Inc.
Column 1 Column 2
0 0
0 0
0 0
0 0
1 0
1 0
1 0
0 0
1 1
0 1
0 0
0 0
0 1
0 1
0 1
0 1
RBS+1 RBS+2 RBS+3
Chapter 11. Memory Controller
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Memory System Interface Example Using UPM
Column 3
RBS+4
Column 4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
11-91