Motorola PowerQUICC II MPC8280 Series Reference Manual page 483

11.4.6.7 External Address Multiplexing Signal
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the
additional delay of multiplexing endangers the device setup time, P/LSDMR[EAMUX]
should be set. Setting this bit causes the memory controller to add another cycle for each
address phase. Figure 11-26 demonstrates the timing when EAMUX equals 1.
Note that EAMUX can also be set in any case of delays on the address lines, such as address
buffers.
CLK
ALE
SDAMUX
CMD
NOP
MA[0–11]
Address setup cycle
11.4.6.8 External Address and Command Buffers (BUFCMD)
In 60x-compatible mode, external buffers may be placed on the command strobes, except
CS, as well as the address lines. If the additional delay of the buffers is endangering the
device setup time, P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory
controller to add one cycle for each SDRAM command. Figure 11-27 illustrates the timing
when BUFCMD equals 1.
CLK
ALE
SDAMUX
CMD strobes
(without cs)
MA[0–11]
CS
Command setup cycle
MOTOROLA
Freescale Semiconductor, Inc.
Act NOP
Row Column
Figure 11-26. EAMUX = 1
Activate NOP
Row Column
Figure 11-27. BUFCMD = 1
Chapter 11. Memory Controller
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Read
Read
Command setup cycle
SDRAM Machine
NOP
NOP
11-45