Motorola PowerQUICC II MPC8280 Series Reference Manual page 1330

Fast Ethernet Registers
Ethernet Event Register (FCCE)/Mask Register (FCCM)
Figure 36-7.
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Table 36-9 describes FCCE/FCCM fields.
Bits Name
0–7 — Reserved, should be cleared.
8 GRA Graceful stop complete. A graceful stop, initiated by the
complete. When the command is issued, GRA is set as soon the transmitter finishes sending a frame
in progress. If no frame is in progress, GRA is set immediately.
9 RXC RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter
finishes sending the current frame, a pause operation is performed.
10 TXC TX control. An out-of-sequence frame was sent.
11 TXE Tx error. An error occurred on the transmitter channel. This event is not maskable via the TxBD[I] bit
12 RXF Rx frame. Set when a complete frame is received on the Ethernet channel. This event is not
maskable via the RxBD[I] bit.
13 BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.
14 TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.
15 RXB Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel.
16–31 — Reserved, should be cleared.
36-24
Freescale Semiconductor, Inc.
—
0000_0000_0000_0000
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)
0000_0000_0000_0000
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Table 36-9. FCCE/FCCM Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10 11
GRA RXC TXC TXE RXF BSY TXB RXB
R/W
—
R/W
Description
GRACEFUL STOP TRANSMIT
12 13 14 15
31
command, is
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