Motorola PowerQUICC II MPC8280 Series Reference Manual page 1257

34.4.6.2 Delay Compensation Buffers (DCB)
Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs
are allocated on a per-link basis. They are of user-definable length, thereby providing a
programmable maximum synchronizable delay. Note that DCBs of links within a group
must all have the same size.
DCBs consist of a circular queue of 64-byte cell buffers. These cell buffers contain the
received cell followed by 12 bytes of header/status information.
Figure 34-27. Cell Buffer in Delay Compensation Buffer
The length of a DCB is defined by the link's DCBSP and DCBEP parameters. The length
of the DCB (defined by (DCBEP-DCBSP)
frame length in bytes, M
boundary. For example, if M = 64, then DCBSP must be on a 4KB boundary. To ensure
group delay synchronization, the minimum length of the DCB should be 2(Mx64).
The DCB memory area must be initialized to zero at link startup.
bits 0-11 bits12-27
IMAEXTBASE
IMAEXTBASE
Figure 34-28. IMA Delay Compensation Buffer
34.4.7 IMA Exceptions
One of the four ATM interrupt queues must be dedicated to IMA events. This enables
minimum latency in dealing with the IMA state machines, and ensures that the unique
MOTOROLA
Freescale Semiconductor, Inc.
52 bytes RX CELL
64 bytes
12 bytes HEADER/STATUS
64. Furthermore, the DCBSP must be aligned on a M
x
IMAEXTBASE
bits 28-31
DCBSP 0000
DCBEP 0000
Chapter 34. Inverse Multiplexing for ATM (IMA)
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16) must be an integer multiple of the IMA
x
IMA External Structure Region
DCB
IMA Programming Model
64-byte
x
M 64-byte boundary
x
(DCBEP - DCBSP) 16
x
34-47