Motorola PowerQUICC II MPC8280 Series Reference Manual page 1310

Features
• Receives back-to-back frames
• Detection of receive frames that are too long
• Multibuffer data structure
• Supports 48-bit addresses in three modes
— Physical. One 48-bit address recognized or 64-bin hash table for physical
addresses
— Logical. 64-bin group address hash table plus broadcast address checking
— Promiscuous. Receives all frames regardless of address (a CAM can be used for
address filtering)
• External CAM support on system bus interfaces
• Special RMON counters for monitoring network statistics
• Transmitter network management and diagnostics
— Lost carrier sense
— Underrun
— Number of collisions exceeded the maximum allowed
— Number of retries per frame
— Deferred frame indication
— Late collision
• Receiver network management and diagnostics
— CRC error indication
— Nonoctet alignment error
— Frame too short
— Frame too long
— Overrun
— Busy (out of buffers)
• Error counters
— Discarded frames (out of buffers or overrun occurred)
— CRC errors
— Alignment errors
• Internal and external loopback mode
• Supports Fast Ethernet in duplex mode
• Supports pause flow control frames
• Support of out-of-sequence transmit queue (for flow-control frames)
• External buffer descriptors (BDs)
36-4
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MPC8280 PowerQUICC II Family Reference Manual
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