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Motorola MPC823e Reference Manual

Microprocessor for mobile computing.
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PowerPC
MPC823e
Reference Manual
The Microprocessor for Mobile Computing
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© 2000 Motorola, Inc. All Rights Reserved.
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   Summary of Contents for Motorola MPC823e

  • Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
  • Page 2 All other trademarks are the property of their respective owners. Acknowledgments The MPC823e Support Team would like to thank the following people for their contribution to the success of the MPC823e: Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,...
  • Page 3: Table Of Contents

    The LCD Controller ............1-10 The PCMCIA-ATA Controller ..............1-10 Power Management ................1-11 System Debug Support ...............1-11 Applications ..................1-11 Differences Between MPC823 (Rev B) and MPC823e .......1-12 MPC823e Glueless System Design ............1-12 Section 2 External Signals The System Bus Signals ...............2-2 Section 3...
  • Page 4 Power Switching Example ..........5-26 5.4.2.2 Register Lock ..............5-27 Low-Power Operation ................. 5-28 Section 6 The PowerPC Core Features ....................6-1 Basic Structure of the Core ..............6-2 6.2.1 Instruction Flow Within the Core ..........6-2 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 5 Atomic Update Primitives ............6-29 6.6.9 Instruction Timing ..............6-30 6.6.10 Stalling Storage Control Instructions ........6-30 6.6.11 Accessing Off-Core Special Registers ........6-30 6.6.12 Storage Control Instructions .............6-31 6.6.13 Exceptions ................6-31 6.6.13.1 DAR, DSISR, and BAR Operation ........6-31 Section 7 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 6 Unsupported Registers ........... 7-6 7.3.2.2 Added Registers ............. 7-6 7.3.3 Storage Model ................7-6 7.3.3.1 Address Translation ............7-6 7.3.4 Reference and Change Bits ............7-7 7.3.5 Storage Protection ..............7-7 7.3.6 Storage Control Instructions ............7-7 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 7 Instruction Execution Timing Instruction Timing List ................8-1 Instruction Execution Timing Examples ..........8-4 8.2.1 Data Cache Load ...............8-4 8.2.2 Writeback ...................8-5 8.2.2.1 Writeback Arbitration ............8-5 8.2.2.2 Private Writeback Bus Load ...........8-6 8.2.3 Fastest External Load (Data Cache Miss) ........8-7 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 8 Programming the Data Cache ............10-3 10.3.1 PowerPC Architecture Instructions .......... 10-3 10.3.1.1 PowerPC User Instruction Set Architecture (Book I) ..10-3 10.3.1.2 PowerPC Virtual Environment Architecture (Book II) ..10-4 10.3.1.3 PowerPC Operating Environment Architecture (Book III) ............... 10-4 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 9 MMU Data Control Register ........11-17 11.6.1.3 MMU Current Address Space ID Register ....11-18 11.6.1.4 MMU Instruction Effective Page Number Register ..11-19 11.6.1.5 MMU Data Effective Page Number Register ....11-20 11.6.1.6 MMU Instruction Real Page Number Register ....11-21 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 10 12.3.3 Programming the Interrupt Controller ........12-7 12.3.3.1 SIU Interrupt Pending Register ........12-7 12.3.3.2 SIU Interrupt Mask Register ......... 12-8 12.3.3.3 SIU Interrupt Edge/Level Register ........ 12-9 12.3.3.4 SIU Interrupt Vector Register ........12-10 viii MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 11 Bus Signal Descriptions ..............13-4 13.4 Bus Interface Operation ..............13-7 13.4.1 Basic Transfers ................13-8 13.4.2 Single Beat Transfers ...............13-8 13.4.2.1 Single Beat Read Flow ..........13-9 13.4.2.2 Single Beat Write Flow ..........13-12 13.4.3 Burst Transfers ...............13-16 13.4.4 The Burst Mechanism ............13-16 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 12 14.4 Setting the Endian Mode Of Operation ..........14-5 Section 15 Memory Controller 15.1 Features ....................15-1 15.2 Architecture ..................15-4 15.3 Register Model ..................15-7 15.3.1 Register Descriptions ............... 15-9 15.3.1.1 Base Registers ............. 15-9 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 13 Control ............15-65 15.5.4.2.9 Disable Timer Mechanism ......15-65 15.5.4.2.10 Last Word ............15-65 15.5.5 The Wait Mechanism ..............15-66 15.5.5.1 Internal and External Synchronous Master ....15-66 15.5.5.2 External Asynchronous Master ........15-67 15.5.5.3 Handling Variable Access Time and Slow Devices ..15-68 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 14 16.2.6.9 RISC Timer Table Algorithm ........16-25 16.2.6.10 Using the Timers to Track Microcontroller Loading ..16-25 16.3 Digital Signal Processing ..............16-26 16.3.1 Features ................. 16-26 16.3.2 DSP Operation ............... 16-26 16.3.2.1 Hardware ..............16-27 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 15 Application Example ........16-53 16.3.4.5 FIR6–Complex C, Real X, and Complex Y ....16-54 16.3.4.5.1 Coefficients and Sample Data Buffers ...16-54 16.3.4.5.2 FIR6 Function Descriptor .......16-55 16.3.4.5.3 FIR6 Parameter Packet ........16-57 16.3.4.6 IIR–Real C, Real X, Real Y .........16-57 MOTOROLA MPC823e REFERENCE MANUAL xiii...
  • Page 16 Timers ....................16-75 16.4.1 Features ................. 16-75 16.4.2 Timer Operation ..............16-76 16.4.2.1 Cascaded Mode ............16-77 16.4.2.2 Timer Global Configuration Register ......16-78 16.4.2.3 Timer Mode Registers ..........16-79 16.4.2.4 Timer Reference Registers ......... 16-80 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 17 The Serial Interface with Time-Slot Assigner ........16-113 16.7.1 Features ................16-115 16.7.2 Configuring the Time-Slot Assigner ........16-115 16.7.3 Enabling Connections to the Time-Slot Assigner ....16-118 16.7.4 Serial Interface RAM Operation ...........16-118 16.7.4.1 One Multiplexed Channel with Static Frames ...16-119 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 18 16.9.7 SCCx Parameter RAM Memory Map ........16-184 16.9.8 Handling Interrupts In the SCCs .......... 16-189 16.9.8.1 Interrupt Handling in the SCC Event Register ..16-189 16.9.8.2 Interrupt Handling in the SCC Mask Register ... 16-189 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 19 16.9.15.20 SCCx UART Status Register ........16-233 16.9.15.21 SCC2 UART Programming Example ......16-233 16.9.15.22 S-Record Programming Example ......16-235 16.9.16 The SCCs In HDLC Mode ............16-236 16.9.16.1 Features ..............16-237 16.9.16.2 SCCx HDLC Channel Frame Transmission Process ..............16-237 MOTOROLA MPC823e REFERENCE MANUAL xvii...
  • Page 20 Exceptions to RFC 1549 ........... 16-273 16.9.19.7 SCCx ASYNC HDLC Implementation ...... 16-273 16.9.19.8 SCCx ASYNC HDLC Parameter RAM Memory Map ............. 16-274 16.9.19.9 Configuring the SCCx ASYNC HDLC Parameters ..16-276 16.9.19.10 SCCx ASYNC HDLC Commands ......16-277 xviii MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 21 SCCx Transparent Parameter RAM Memory Map ..16-307 16.9.21.6 SCCx Transparent Commands .........16-307 16.9.21.7 SCCx Transparent Controller Errors ......16-309 16.9.21.8 SCCx Transparent Mode Register ......16-309 16.9.21.9 SCCx Transparent Receive Buffer Descriptor ..16-310 16.9.21.10 SCCx Transparent Transmit Buffer Descriptor ..16-312 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 22 Features ..............16-319 16.9.22.2 Ethernet On the MPC823e ........16-320 16.9.22.3 Understanding Ethernet on the MPC823e ....16-321 16.9.22.4 Connecting the MPC823e to the EEST ....16-321 16.9.22.5 SCCx Ethernet Channel Frame Transmission Process ..............16-323 16.9.22.6 SCCx Ethernet Channel Frame Reception Process ..............
  • Page 23 Sending a Preamble ..........16-397 16.11.6.9 SMCx UART Controller Errors ........16-397 16.11.6.10 SMCx UART Mode Register ........16-398 16.11.6.11 SMCx UART Receive Buffer Descriptor ....16-399 16.11.6.12 SMCx UART Transmit Buffer Descriptor ....16-403 16.11.6.13 SMCx UART Event Register ........16-405 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 24 SMCx GCI Mask Register ........16-433 16.12 The Serial Peripheral Interface ............16-433 16.12.1 Features ................16-434 16.12.2 SPI Clocking and Pin Functions ........... 16-435 16.12.3 The SPI Transmission and Reception Process ....16-436 16.12.3.1 MultiMaster Operation ..........16-437 xxii MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 25 C Event Register ............16-475 16.13.7.8 C Mask Register .............16-476 16.13.8 C Controller Initialization Sequence ........16-476 16.14 The Parallel I/O Ports ..............16-477 16.14.1 Features ................16-478 16.14.2 Port A Pin Functionality ............16-478 16.14.3 The Port A Registers ............16-480 MOTOROLA MPC823e REFERENCE MANUAL xxiii...
  • Page 26 CPM Interrupt Mask Register ........16-509 16.15.5.4 CPM Interrupt In-Service Register ......16-510 16.15.5.5 CPM Interrupt Vector Register ......... 16-511 16.15.6 Interrupt Handling Examples ..........16-511 16.15.6.1 PC6 Interrupt Handler Example ........ 16-511 16.15.6.2 USB Interrupt Handler Example ....... 16-512 xxiv MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 27 Types of LCD Interfaces ............18-3 18.1.2.1 Passive LCD Interface ..........18-4 18.1.2.2 Active LCD Interface .............18-5 18.1.2.3 Smart Panel LCD Interface ...........18-5 18.2 The MPC823e LCD Controller ............18-6 18.3 LCD Controller Operation ..............18-8 18.3.1 FIFO Control ................18-9 18.3.2 Pixel Generation ..............18-10 18.3.2.1 Grayscale ..............18-10...
  • Page 28 Video Controller Configuration Register ........19-5 19.3.2 Video Status Register .............. 19-7 19.3.3 Video Command Register ............19-8 19.3.4 Video Background Color Buffer Register ......... 19-9 19.3.5 Video Frame Configuration Register (Set 0) ......19-10 xxvi MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 29 20.3.1 Internal Watchpoints and Breakpoints ........20-9 20.3.1.1 Restrictions ..............20-12 20.3.1.2 Byte And Half-Word Working Modes ......20-12 20.3.1.3 Context-Dependent Filter ..........20-14 20.3.1.4 Ignore First Match Option ...........20-15 20.3.1.5 Generating Compare Types ........20-15 20.3.2 Basic Operation ..............20-16 MOTOROLA MPC823e REFERENCE MANUAL xxvii...
  • Page 30 Load/Store Support Comparators Control Register..20-48 20.6.2.7 Load/Store Support AND-OR Control Register ..20-50 20.6.2.8 Breakpoint Counter A Value and Control Register ..20-53 20.6.2.9 Breakpoint Counter B Value and Control Register ..20-54 20.6.3 Debug Mode Registers ............20-55 xxviii MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 31 The sample/preload Instruction ..........21-20 21.3.3 The bypass Instruction ............21-20 21.3.4 The clamp Instruction .............21-20 21.3.5 The hi-z Instruction ..............21-20 21.4 MPC823e Restrictions ..............21-21 Section 22 DC Electrical Specifications 22.1 Maximum Ratings (GND = 0V) ............22-1 22.2 Thermal Characteristics ..............22-2 22.3 Power Considerations .................22-2...
  • Page 32 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Example #3 ...................A-4 Appendix B MPC823e Instruction Set Instruction Formats ................B-1 Split-Field Notation ................B-1 Instruction Fields ...................B-2 Notations and Conventions ..............B-3 The MPC823e Instruction Set ...............B-6 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 33 5-11. BRGCLK Divider ....................5-19 5-12. SYNCCLK Divider ..................5-20 5-13. LCDCLK Divider .....................5-21 5-14. LCD Clock Timing Diagram ................5-21 5-15. MPC823e Power Rails and TEXP Status ............5-24 5-16. External Power Supply Scheme ..............5-26 5-17. Register Lock Mechanism ................5-28 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 34 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 5-18. MPC823e Low-Power Mode Flowchart ............5-29 Section 6 The PowerPC Core 6-1. Block Diagram of the Core ................6-3 6-2. Instruction Flow Conceptual Diagram .............. 6-3 6-3. Basic Instruction Pipeline Timing Diagram ............6-4 6-4.
  • Page 35 11-4. Organization of the Memory Management Unit Registers ......11-15 Section 12 System Interface Unit 12-1. System Configuration and Protection Logic ...........12-4 12-2. MPC823e Interrupt Structure .................12-5 12-3. Interrupt Table Handling Example ..............12-11 12-4. Real-Time Clock Block Diagram ..............12-17 12-5. Periodic Interrupt Timer Block Diagram ............12-22 12-6.
  • Page 36 15-11. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 10 or 11, SCY = 0, CSNT = 1, and TRLX = 1) ............15-33 15-12. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 00, SCY = 0, CSNT = 1, and TRLX = 1) ................15-34 15-13.
  • Page 37 15-54. EDO DRAM Burst Read Access ..............15-92 15-55. EDO DRAM Burst Write Access ..............15-93 15-56. EDO DRAM Refresh Cycle (CAS Before RAS) ...........15-94 15-57. EDO DRAM Exception Cycle ...............15-95 15-58. Blank Worksheet for a UPM .................15-96 MOTOROLA MPC823e REFERENCE MANUAL xxxv...
  • Page 38 16-36. SDMA Data Paths ..................16-83 16-37. SDMA Bus Arbitration .................. 16-84 16-38. IDMA Buffer Descriptor Ring ................ 16-91 16-39. Single-Address, Peripheral Write, Asynchronous TA ........ 16-103 16-40. Single-Address, Peripheral Write, Synchronous TA ........16-104 xxxvi MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 39 16-76. SCC2 UART Receive Buffer Descriptor Example ........16-221 16-77. SCCx UART Interrupt Event Example ............16-227 16-78. SCCx HDLC Framing Structure ..............16-234 16-79. HDLC Address Recognition Example ............16-238 16-80. SCC2 HDLC Receive Buffer Descriptor Example ........16-245 16-81. HDLC Interrupt Event Example ..............16-251 MOTOROLA MPC823e REFERENCE MANUAL xxxvii...
  • Page 40 16-87. Delayed RTSx Mode .................. 16-263 16-88. HDLC Bus Time-Slot Assigner Transmission Line Configuration ....16-263 16-89. LocalTalk Frame Format ................16-265 16-90. Connecting the MPC823e to AppleTalk ............. 16-267 16-91. ASYNC HDLC Frame Structure ..............16-270 16-92. Reception Flowchart .................. 16-272 16-93.
  • Page 41 16-131.Byte Read from Device without Internal Addresses ........16-460 16-132.I C Memory Format ...................16-467 16-133.Parallel Block Diagram For PA15 ..............16-482 16-134.Parallel Block Diagram For PA14 ..............16-483 16-135.MPC823e Interrupt Structure ..............16-499 16-136.Interrupt Request Masking ................16-504 Section 17 PCMCIA Interface 17-1. System with One PCMCIA Socket ..............17-2 17-2.
  • Page 42 18-2. LCD Subsystem ..................... 18-3 18-3. Passive Interfaces ..................18-4 18-4. Active (TFT) Interface ..................18-5 18-5. The MPC823e LCD System ................18-6 18-6. LCD Controller Block Diagram ............... 18-7 18-7. LCD Functional Module ................. 18-8 18-8. Grayscale Generation .................. 18-11 18-9.
  • Page 43 21-2. TAP Controller State Machine ................21-3 21-3. Output Pin Cell (O.Pin) ...................21-4 21-4. Observe-Only Input Pin Cell (I.Obs) ...............21-5 21-5. Output Control Cell (IO.CTL) ................21-5 21-6. General Arrangement of Bidirectional Pin Cells ..........21-6 21-7. Bypass Register ...................21-20 MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 44: List Of Tables

    External Signals 2-1. Signal Descriptions ..................2-2 2-2. Pin Breakout ....................2-13 Section 3 Memory Map 3-1. MPC823e Internal Memory Map ..............3-1 Section 4 Reset 4-1. Possible Reset Results ..................4-1 Section 5 Clocks and Power Control 5-1. Power-On Reset Clock Configuration ............5-13 5-2.
  • Page 45 13-3. Data Bus Contents for Write Cycles .............13-27 13-4. BURST/TSIZE Encoding ................13-33 13-5. Address Space Definitions ................13-34 13-6. Termination Signal Protocol .................13-46 Section 14 Endian Modes 14-1. Little-Endian Effective Address Modification For Individual Aligned Scalar ......................14-1 MOTOROLA MPC823e REFERENCE MANUAL xliv...
  • Page 46 16-11. FIR5 Parameter Packet ................16-53 16-12. FIR6 Parameter Packet ................16-57 16-13. IIR Parameter Packet ................... 16-59 16-14. MOD Parameter Packet ................16-62 16-15. DEMOD Parameter Packet ................16-64 16-16. LMS1 Parameter Packet ................16-67 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 47 16-45. Prioritization of CPM Interrupt Sources ............16-507 16-46. Encoding the Interrupt Vector ..............16-510 Section 17 PCMCIA Interface 17-1. Card Enable as Driven by the MPC823e ............17-3 17-2. Host Programming for Memory Cards ............17-7 17-3. Host Programming For I/O Cards ..............17-7 Section 18LCD Controller 18-1.
  • Page 48 20-12. Development Support Register Protection ........... 20-41 Section 21 IEEE 1149.1 Test Access Port 21-1. Boundary Scan Bit Definition ................. 21-7 21-2. Instruction Decoding ..................21-19 Appendix A Serial Communication Performance A-1. MPC823e Performance Table .................A-3 xlvii MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 49: Features

    SECTION 1 INTRODUCTION The MPC823e microprocessor is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of portable electronic products. It is a version of the low-cost MPC823 with larger instruction and data caches, which will provide for greater PowerPC core performance.
  • Page 50 DSP Functions are Supported by ROM or Download Microcode and the Communication Processor Module DSP Capabilities, Include but are No Limited to JPEG Compression/Decompression • Four Independent Baud Rate Generators and Two Input Clock Pins for Supplying Clocks to the SCC and SMC Serial Channels MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 51 • Four Independent 16-Bit Timers That can be Configured as Two 32-Bit Timers. • Interrupts Seven External Interrupt Request (IRQ) Lines One Nonmaskable Interrupt Twelve Port Pins with Interrupt Capability Ten Internal Interrupt Sources Programmable Highest Priority Request MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 52 — Supports Interlace/Noninterlace Scanning Methods — Programmable Display Active Area — Programmable Background Color for Inactive Area — Glueless Interface for Most Digital Video Encoders — Uses Burst Read DMA Cycles for Maximum Bus Performance — End-of-Frame Interrupt Generation MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 53 Power-Down—All Units are Disabled Including PLL, but not the Real-Time Clock and Periodic Interrupt Timer, Timebase, and Decrementer. Saves More Power than Other Modes. The State of Certain Registers may be Preserved. Can be Dynamically Shifted Between High and Low Frequency Operation MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 54: Architecture

    I/O support needed for high-speed digital communications. The MPC823e is comprised of four main modules that interface with the 32-bit internal bus: • The embedded PowerPC core •...
  • Page 55 Introduction Figure 1-1. MPC823e Block Diagram MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 56: The Embedded Powerpc Core

    32K and 256M. The memory controller has 0 to 20 wait states for each bank of memory and can use address type matching to qualify each memory bank access. It provides four byte-enable signals for varying width devices, one output-enable signal, and one boot chip-select that is available at reset. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 57: The Communication Processor Module

    The DRAM controller supports page mode access for successive transfers within bursts. Although the MPC823e supports a glueless interface to DRAM, the capacitance of the system bus may require that there be external buffers. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking for a maximum of seven refresh cycles.
  • Page 58: The Video/lcd Controller

    Introduction 1.2.4 The Video/LCD Controller The MPC823e has a dual-purpose video/LCD controller that shares common dual-port memory. You can only run one of the controllers at a time. 1.2.4.1 THE VIDEO CONTROLLER. The video controller can be used to drive a digital NTSC/PAL encoder or a wide variety of digital LCD panels.
  • Page 59: Power Management

    The MPC823e microprocessor can compare using the =, ≠, <, and > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events.
  • Page 60: Differences Between Mpc823 (rev B) And Mpc823e

    • A time-division multiplex channel (TDMB) was added to the serial interface 1.8 MPC823e GLUELESS SYSTEM DESIGN The MPC823e was primarily designed to make it easy for you to interface a microprocessor with other system components. Figure 1-2 illustrates a system configuration that contains one flash EPROM and yet supports DRAM SIMM and one SRAM.
  • Page 61 Introduction 8-BIT BOOT EPROM/FLASH ADDRESS ADDRESS GPL1/ 0:3] DATA DATA DRAM MPC823e ADDRESS [0:3] DATA PARITY[0:3] PARITY[0:3] SRAM ADDRESS DATA Figure 1-2. MPC823e System Configuration MOTOROLA MPC823e REFERENCE MANUAL 1-13...
  • Page 62: External Signals

    SECTION 2 EXTERNAL SIGNALS This section briefly describes each of the MPC823e input and output signals. VDDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS/KAPWR A[6:31] USBRXD/PA[15] TSIZ0/REG USBOE/PA[14] TSIZ1 RXD2/PA[13] RD/WR TXD2/PA[12] BURST SMRXD2/L1TXDA/PA[9] BDIP/GPL_B5 SMTXD2/L1RXDA/PA[8] TIN1/L1RCLKA/BRGO1/CLK1/PA[7] TIN3/L1RCLKB/TOUT1/CLK2/PA[6] TIN2/L1TCLKA/BRGO2/CLK3/PA[5] TIN4/L1TCLKB/TOUT2/CLK4/PA[4] IRQ2/RSV LCD_A/SPISEL/PB[31] IRQ4/KR/RETRY/SPKROUT SPICLK/TXD3/PB[30] SPIMOSI/RXD3/PB[29] D[0:31] BRGO3/SPIMISO/PB[28]...
  • Page 63: The System Bus Signals

    This signal is driven by the MPC823e when it is the owner of the bus. It is input when an external master initiates a transaction on the bus and it is sampled internally to allow the memory controller/PCMCIA interface to control the accessed slave device.
  • Page 64 Transfer Error Acknowledge —This open-drain signal indicates that a bus error occurred in the current transaction. It is driven asserted by the MPC823e when the bus monitor does not detect a bus cycle termination within a reasonable amount of time.
  • Page 65 D[16:23] by transferring to a slave device initiated by IRQ5 the MPC823e. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus.
  • Page 66 PCMCIA Slot B are handled by the PCMCIA interface. Write Enable 0 —This output signal is asserted when a write access to an external slave controlled by the GPCM in the memory controller is initiated by the MPC823e. BS_AB0...
  • Page 67 Address Strobe —This input pin is driven by an external asynchronous master to indicate a valid address on the A[6:31] lines. The memory controller in the MPC823e will synchronize this signal and control the memory device addressed if it is recognized to be under its control.
  • Page 68 IP_B0 Input Port B 0 —This input signal is sensed by the MPC823e and its value and changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
  • Page 69 PIN NUMBER DESCRIPTION IP_B6 Input Port B 6—This input signal is sensed by the MPC823e and its value and changes are reported in the PIPR and PSCR registers of the PCMCIA interface. DSDI Development Serial Data Input—This input signal is the data in for the debug port interface.
  • Page 70 CTS3—The Clear to Send Modem line for serial communication controller 3. SDACK1 SDACK1—The SDMA acknowledge 1 output pin that is used as a peripheral L1RSYNCB interface signal for IDMA emulation. L1RSYNCB—The transmit sync input for the serial interface time-division multiplex port B. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 71 CTS2—The Clear to Send Modem line for serial communication controller 2. PC[8] General-Purpose I/O Port C Bit 8—Bit 8 of the general-purpose I/O port C. CD2—The Carrier Detect Modem line for serial communication controller 2. TGATE1 TGATE1—The timer1/timer2 gate signal. 2-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 72 General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose I/O port D. LD0—One of the 12 data bus bits used to drive the LCD panel. FIELD FIELD—The line the video controller uses to signal which of the two fields is the current one. MOTOROLA MPC823e REFERENCE MANUAL 2-11...
  • Page 73 Development Serial Data Output—This output signal is the data out of the debug port interface. TRST Test Reset—This input signal is the asynchronous reset of the TAP machine on the JTAG interface. See Table 2-2 No Connect—These pins are not connected. for pin breakout. 2-12 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 74 External Signals Table 2-2. Pin Breakout SIGNAL PIN NUMBER ADDRESS BUS PINS MOTOROLA MPC823e REFERENCE MANUAL 2-13...
  • Page 75 External Signals Table 2-2. Pin Breakout (Continued) SIGNAL PIN NUMBER DATA BUS PINS 2-14 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 76 G5, G12, H5, H12, J5, J12, K5, K12, L5, L12, M5–M12 VDDL A7, G1, J16, T7 VDDSYN KAPWR VSSSYN VSSSYN1 F6–F11, G6–G11, H6–H11, J6–J11, K6–K11, L6–L11 NO CONNECT PINS A16, C1, C6, E14, J13, N9, N13, P1, P10 MOTOROLA MPC823e REFERENCE MANUAL 2-15...
  • Page 77: Memory Map

    SECTION 3 MEMORY MAP This section discusses the internal memory map (including key registers) of the MPC823e. Each memory resource is mapped within a contiguous block of 16K storage. The location of this block within the global 4G real storage space can be mapped on 64K resolution through an implementation specific special register called the internal memory map register (IMMR).
  • Page 78 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION POR3—PCMCIA Interface Option Register 3 17-17 PBR4—PCMCIA Interface Base Register 4 17-16 POR4—PCMCIA Interface Option Register 4 17-17 PBR5—PCMCIA Interface Base Register 5 17-16 POR5—PCMCIA Interface Option Register 5...
  • Page 79 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION BR7—Base Register Bank 7 15-9 OR7—Option Register Bank 7 15-11 140 to 163 RES—Reserved — — MAR—Memory Address Register 15-26 MCR—Memory Command Register...
  • Page 80 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SYSTEM INTEGRATION TIMERS KEYS TBSCRK—Timebase Status and Control Register Key 5-27 TBREFFUK—Timebase Reference Register Upper Key 5-27 TBREFFLK—Timebase Reference Register Lower Key 5-27 TBK—Timebase and Decrementer Register Key...
  • Page 81 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION VFCR1—Video Frame Configuration Register (Set 1) 19-13 VFAA1—Video Frame Buffer A Start Address Register (Set 1) 19-14 VFBA1—Video Frame Buffer B Start Address Register (Set 1)
  • Page 82 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION IDMR1—IDMA1 Mask Register 16-95 915 to 917 RES—Reserved — — IDSR2—IDMA2 Status Register 16-94 919 to 91B RES—Reserved — — IDMR2—IDMA2 Mask Register...
  • Page 83 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION CPM TIMERS TGCR—Timer Global Configuration Register 16-77 982 to 98F RES—Reserved — — TMR1—Timer1 Mode Register 16-78 TMR2—Timer2 Mode Register 16-78 TRR1—Timer1 Reference Register 16-79 TRR2—Timer2 Reference Register...
  • Page 84 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION RCTR3—RISC Controller Trap Register 3 — RCTR4—RISC Controller Trap Register 4 — 9D4 to 9D5 RES—Reserved — — RTER—RISC Timer Event Register...
  • Page 85 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL COMMUNICATION CONTROLLER 2 GSMR_L—SCC2 General Mode Low Register 16-166 GSMR_H—SCC2 General Mode High Register 16-166 PSMR—SCC2 Protocol-Specific Mode Register 16-176 16-217 (UART)
  • Page 86 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SCCE—SCC3 Event Register 16-187 16-227 (UART) 16-250 (HDLC) 16-284 (AHDLC) 16-314 (Trans) A52-A53 Reserved — SCCM—SCC3 Mask Register 16-187 16-229 (UART) 16-253 (HDLC)
  • Page 87 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL PERIPHERAL INTERFACE SPMODE—SPI Mode Register 16-443 RES—Reserved — SPIE—SPI Event Register 16-452 AA7 to AA9 RES—Reserved — — SPIM—SPI Mask Register 16-453 RES—Reserved...
  • Page 88 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION DUAL-PORT RAM 2000 to 2FFF DPRAM—Dual-Port RAM 4,096 bytes — 3000 to 3BFF DPRAM—Dual-Port RAM Expansion — — 3C00 to 3FFF PRAM—Parameter RAM 1,024 bytes —...
  • Page 89: Reset

    SECTION 4 RESET The reset block of the MPC823e has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
  • Page 90: Types Of Reset

    When PORESET is asserted, the MPC823e enters the power-on reset (POR) state in which SRESET and HRESET are asserted by the core. When the MPC823e remains in POR, the extension counter of 512 is reset, and the MODCK pins are sampled when POR pin is negated.
  • Page 91: External Hard Reset

    Reset 4.1.2 External Hard Reset HRESET (hard reset) is a bidirectional, active low I/O pin. The MPC823e can only detect an external assertion of HRESET if it occurs while the MPC823e is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft reset) is a bidirectional, active low I/O pin.
  • Page 92: External Soft Reset

    Trace Window End Address for more information. If the DSCK pin is asserted during SRESET negation, the processor will take a breakpoint exception and go directly to debug mode, instead of fetching the reset vector. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 93: Reset Status Register

    The 32-bit reset status register (RSR) is powered by the keep-alive power supply. As shown in Section 3 Memory Map , it is memory-mapped into the MPC823e system interface unit register map and receives its default reset values at power-on reset.
  • Page 94 1, but a write of zero has no effect on it. 0 = No JTAG reset event occurred. 1 = A JTAG reset event occurred. Bits 8–31—Reserved These bits are reserved and must be set to 0. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 95: How To Configure Reset

    4.3.1 Hard Reset When a hard reset event occurs, the MPC823e reconfigures its hardware system as well as the development port configuration. The logical value of the bits that determine its initial mode of operation are sampled either from the data bus or from an internal default constant (D[0:31]=x’00000000).
  • Page 96 RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-2. Reset Configuration Sampling Scheme For Short PORESET Assertion CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-3. Reset Configuration Sampling Scheme For Long PORESET Assertion MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 97 Reset MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 98: Hard Reset Configuration Word

    1 = The memory controller is not activated after reset, but it is cleared. BPS—Boot Port Size This field defines the port size of the boot device. 00 = 32-bit port size. 01 = 8-bit port size. 10 = 16-bit port size. 11 = Reserved. 4-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 99 IP_B3/IWP2/VF2 functions as VF2. IP_B4/LWP0/VF0 functions as VF0. IP_B5/LWP1/VF1 functions as VF1. OP2/MODCK1/STS functions as STS. ALE_B/DSCK/AT1 functions as AT1. IP_B2/AT2 functions as AT2. IP_B6/DSDI/AT0 functions as AT0. IP_B7/PTR/AT3 functions as AT3. OP3/MODCK2/DSDO functions as OP3. MOTOROLA MPC823e REFERENCE MANUAL 4-11...
  • Page 100: Soft Reset

    The EBDF bits (described in Section 5.2.1 System Clock and Reset Control Register ) are initialized during HRESET using the hard reset configuration mechanism. 4.3.2 Soft Reset When a soft reset event occurs, the MPC823e reconfigures the development port. 4-12 MPC823e REFERENCE MANUAL...
  • Page 101: Clocks And Power Control

    MPC823e clock module. For additional timer information, refer to Section 12 System Interface Unit . The MPC823e has a variety of programmable modes that allow your system to operate at its highest level, and yet it still gives you the option of operating in a power-saving mode.
  • Page 102 (÷4 OR ÷16 ) DIVIDERS CLOCK BRGCLK DRIVERS LCDCLK SYNCCLK CLKOUT CLKOUT DRIVER TBCLK TMBCLK TMBCLK DRIVER RTDIV RTSEL ÷4 RTC /PIT CLOCK PITRTCLK AND DRIVER XTAL MAIN CLOCK EXTAL ÷512 OSCILLATOR (OSCM) Figure 5-1. Clock Source and Distribution MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 103: Register Model

    5.2 REGISTER MODEL 5.2.1 System Clock and Reset Control Register The SPLL has a 32-bit control register that is powered by keep-alive power. The system clock and reset control register (SCCR) is memory-mapped into the MPC823e system interface unit’s register map. SCCR...
  • Page 104 1 = The system switches to high frequency when there is a pending interrupt from the interrupt controller or POW bit in the machine state register is cleared. Bits 11–12 and 15–16—Reserved These bits are reserved and must be set to 0. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 105 This field sets the VCOOUT frequency division factor for general system clocks to be used in low-power mode. In low-power mode, the MPC823e automatically switches to the DFNL frequency. To select the DFNL frequency, load this field with the divide value and set the CSRC bit.
  • Page 106 This field sets the VCOOUT frequency division factor for general system clocks to be used in normal mode. In normal mode, the MPC823e automatically switches to the DFNH frequency. To select the DFNH frequency, load this field with the divide value and clear the CSRC bit.
  • Page 107: Pll, Low-power, And Reset Control Register

    DFNH bits is 0x0 (divide-by-one). When the SPLL is operating in one-to-one mode, the MF field is set to 0. See Table 5-2 for details. Bits 12–15—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 108 This bit specifies whether the DFNH or DFNL field generates the general system clock. This bit is cleared by a hard reset. 0 = The general system clock is generated by the DFNH field. 1 = The general system clock is generated by the DFNL field. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 109 This bit indicates when the address and data external pins are driven by an internal pull-down device in sleep and deep-sleep mode. 0 = No pull-down on the address and data bus. 1 = Address and data bus is driven low in sleep and deep-sleep mode. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 110: The Clock Module

    The MPC823e clock module consists of the main crystal oscillator, the SPLL, the low-power divider, the clock generator/driver blocks, and the clock module/system low-power control block.
  • Page 111 DFNH GCLK1 GCLK2 UPM, PCMCIA, DFNL EXTERNAL GCLK1_50 EBDF INTERFACE PHASE GCLK2_50 LOW-POWER MODE CLKOUT COM[0:1] LCDCLK LCD/VIDEO CONTROLLER LCDCLK50 DFLCD DFALCD LCD PANEL DIVISION FACTOR TOTAL LESS THAN 64 Figure 5-3. Clock Module Diagram MOTOROLA MPC823e REFERENCE MANUAL 5-11...
  • Page 112: On-chip Oscillators And External Clock Input

    Lower frequency clock input reduces the overall electromagnetic interference generated by the system. Also, oscillating at different frequencies reduces the cost because you will not have to add more oscillators to your system. The MPC823e SPLL block diagram is illustrated in Figure 5-4.
  • Page 113: Spll Stability

    For input frequencies greater than 15MHz and MF ≤ 2, this skew is between -0.9ns and +0.9ns. Otherwise, this skew is not guaranteed. However, for MF<10 and input frequencies greater than 10MHz, the skew is between -2.3ns and +2.3ns. MOTOROLA MPC823e REFERENCE MANUAL 5-13...
  • Page 114: The Low-power Clock Divider

    SYNCCLK, LCDCLK, LCDCLK50, BRGCLK, and GCLKx (which is sent to the rest of the MPC823e). GCLKxC is the system timing reference for the core, instruction and data caches, and memory management unit. GCLKx is the system timing reference for the other modules.
  • Page 115 The low-power dividers allow you to reduce and restore the operating frequencies of different sections of the MPC823e without losing the SPLL lock. Using the low-power dividers, you can still obtain full chip operation, but at a lower frequency. This is called normal low mode.
  • Page 116: Internal Clock Signals

    GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50—are the basic clocks supplied to all modules of the MPC823e. GCLKxC is supplied to the core, data and instruction caches, and memory management unit. It is not active when the core is in sleep or power-down mode.
  • Page 117 EBDF bit in the SCCR. GCLK2_50 always rises simultaneously with GCLK2. GCLK1_50 rises simultaneously with GCLK1, but when the MPC823e is not in normal low mode, the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50 and EBDF determines the division factor between GCLKx and GCLKx_50.
  • Page 118 GCLK1 DIVIDED BY 4 GCLK2 DIVIDED BY 4 Figure 5-8. Divided System Clocks Timing Diagram GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 5-9. MPC823e Clocks For Division Factor 2 5-18 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 119 MPC823e is operating at a reduced frequency. Refer to Section 16.8 The Baud Rate Generators for more information about using the baud rate generator clock to save power.
  • Page 120: The Baud Rate Generator Clock

    MPC823e is operating at a reduced frequency. This allows you to maintain the serial synchronization circuitry at the preferred rate, while lowering the general system clock to the lowest possible rate.
  • Page 121: The Lcd Clocks

    LCDCLK DIVIDE BY 1 LCDCLK50 DIVIDE BY 1 GCLK2 DIVIDE BY 2 LCDCLK DIVIDE BY 2 LCDCLK50 DIVIDE BY 2 GCLK2 DIVIDE BY 4 LCDCLK DIVIDE BY 4 LCDCLK50 DIVIDE BY 4 Figure 5-14. LCD Clock Timing Diagram MOTOROLA MPC823e REFERENCE MANUAL 5-21...
  • Page 122: Clock Configuration

    Clocks and Power Control 5.3.5 Clock Configuration You can configure the clock of the MPC823e using the MODCK1 and MODCK2 pins. The SPLL has several power and ground pins (VDDSYN, VSSSYN, VSSSYN1, and XFC) that must be properly terminated for stability and CLKOUT integrity.
  • Page 123: The System Phase-locked Loop Pins

    5.3.5.2 THE SYSTEM PHASE-LOCKED LOOP PINS. The internal frequency of the MPC823e and the output of the CLKOUT pin depends on the quality of the crystal circuit and the MF bit in the PLPRCR. The SPLL contains the following dedicated pins that are isolated from common power and ground.
  • Page 124: Power Control

    Clocks and Power Control 5.4 POWER CONTROL To preserve the life of your battery, the MPC823e provides low-power modes that limit the operation to essential modules. In addition to normal high mode, the MPC823e supports normal low, doze high, doze low, sleep, deep-sleep, and power-down modes. When the communication processor module is idle, it uses its own power-saving mechanism to shut down automatically.
  • Page 125: Keep-alive Power

    5% in power-down mode 5.4.2 Keep-Alive Power When the MPC823e is in normal operation mode, the keep-alive power supply (KAPWR) is powered to the same voltage value as that of the I/O buffers and logic. Therefore, if the VDDL and VDDH is 3.3V, then the KAPWR is 2.9V to 3.3V.
  • Page 126: Power Switching Example

    If VDDL is fed with 3.3V, SW2 and SW3 can be combined into one switch. The TEXP pin, if enabled, is asserted by the MPC823e when the real-time clock or timebase time value matches the value programmed in its associated alarm register or when the periodic interrupt timer or decrementer decrements their value to zero.
  • Page 127 Clocks and Power Control 5.4.2.2 REGISTER LOCK. The MPC823e registers that are powered by KAPWR can be write-protected using the associated key register shown in Table 5-6. When the MPC823e disconnects from the main power supply after it enters power-down mode, the value of these registers is automatically preserved.
  • Page 128: Low-power Operation

    The PLPRCR is described in Section 5.2.2 PLL, Low-Power, and Reset Control Register . The MPC823e uses an interrupt to exit from any of these lower power modes. An enabled interrupt clears the LPM field, but does not change the CSRC bit. An interrupt switches automatically to normal high mode from normal low, doze high, doze low, sleep, or deep-sleep mode.
  • Page 129 ** TEXPS RECEIVES THE ZERO VALUE BY WRITING A ONE TO IT. WRITING A ZERO HAS NO EFFECT ON TEXPS. *** YOU CAN SWITCH FROM NORMAL HIGH TO NORMAL LOW ONLY IF THE CONDITIONS TO AN INTERRUPT ARE CLEARED. Figure 5-18. MPC823e Low-Power Mode Flowchart MOTOROLA...
  • Page 130 GCLK1 clocks. Once the interrupt is recognized, it takes between two and four GCLK1 clocks for the MPC823e to reach normal high mode. For example, it could take between 10.24µs and 20.48µs to wake up in a 75MHz system where DFNL = 111 (divided by 256).
  • Page 131 In normal and doze modes, the system can be in the high mode defined by the DFNH field or in the low mode defined by the DFNL field. The MPC823e is in normal high mode after reset and this also the default state when the condition to exit low-power mode occurs.
  • Page 132: The Powerpc Core

    In addition, it contains part of the development support features of the MPC823e, including breakpoint and watchpoint support, program flow tracking data generation, and debug mode operation in which the core is controlled by the development support system through the debug port module.
  • Page 133: Basic Structure Of The Core

    The instruction queue is always flushed when the history buffer is recovered. An instruction retires from the machine after it finishes executing without exception and all preceding instructions are retired from the machine. Figure 6-1 illustrates the core’s microarchitecture. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 134 (32 X 32) HISTORY IDIV ADDR DATA SOURCE BUSES (4 SLOTS / CLOCK) Figure 6-1. Block Diagram of the Core RETIRE EXECUTION UNITS WRITEBACK HISTORY BUFFER ISSUE BRANCH INSTRUCTION QUEUE UNIT FETCH Figure 6-2. Instruction Flow Conceptual Diagram MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 135: Basic Instruction Pipeline

    The sequencer data path is illustrated in Figure 6-4. In addition, the sequencer implements all branch processor instructions, including flow control and condition register instructions. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 136: Flow Control

    Branches enter the queue to mark watchpoints. See Section 20 Development Capabilities and Interface for details. Since branches do not prevent the issue of sequential instructions unless they come in pairs, the performance impact of entering branches in the instruction prefetch queue is negligible. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 137: Issuing Instructions

    The execution units then decode the instruction, interrogate the register unit (if the operands and targets are free), and inform the sequencer that it accepts the instruction for execution. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 138: Interrupts

    The core interrupts can be generated when an exception occurs. An exception results when certain instructions are executed or an asynchronous external event occurs. There are five exception sources in the MPC823e: • External interrupt request • Certain memory access conditions (protection faults and bus error) •...
  • Page 139: Implementing The Precise Exception Model

    Instructions remain in the queue until they complete execution and all preceding instructions have been completed to a point where no exception can be generated (in the core, such a condition is fulfilled by waiting for full completion). MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 140 If so, instruction issue waits until the long latency operation finishes. The following types of instructions can potentially cause the history buffer to fill: • Floating-point arithmetic instructions • Integer divide instructions • Instructions that affect or use resources external to the core (load/store instructions) MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 141: Restartability After An Interrupt

    A write of any data to these locations performs the operation specified in the following table. Any read from these locations is treated like any other unimplemented instruction and, therefore, results in an implementation-dependent software emulation interrupt. 6-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 142: Processing An Interrupt

    At time point E the machine state register and instruction pointer of the executing process have been saved and control has been transferred to the interrupt handler routine. MOTOROLA MPC823e REFERENCE MANUAL 6-11...
  • Page 143: Serialization

    This can be either divide, load, or store a multiple, string, or pair of simple load/store instructions. 6-12 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 144: The External Interrupt

    6.3.7 The External Interrupt The core provides one external interrupt line: the architectural maskable external interrupt. In the MPC823e, this interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by the MSR bit, which is automatically cleared by the hardware to disable external interrupts when any interrupt is taken.
  • Page 145: Interrupt Ordering

    NOTES: The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second instruction. This, of course, refers to this second instruction. Exclusive for any one instruction. 6-14 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 146: The Register Unit

    • Decodes the operand fields of all sequential instructions • Drives the operand buses, as requested by the execution unit • Performs scoreboard checking and signing • Samples the resulting data from the writeback bus MOTOROLA MPC823e REFERENCE MANUAL 6-15...
  • Page 147: Control Registers

    The PowerPC Core 6.4.1 Control Registers The following tables describe the core control registers, also known as special-purpose registers, implemented within the MPC823e. Table 6-7. Standard Special-Purpose Registers REGISTER PRIVILEGED SERIALIZE ACCESS NAME DECIMAL 00000 00001 Write: Full Sync Read:...
  • Page 148 Synch Relative to Load/Store Operations 00100 11110 ICTRL Debug Fetch Sync on Write 00100 11111 Debug Write: Fetch Sync Read: Synch Relative to Load/Store Operations 10011 10110 DPDR Debug Read and Write 10011 10111 Fetch DPIR MOTOROLA MPC823e REFERENCE MANUAL 6-17...
  • Page 149 Refer to Section 20.6.2 Development Port Registers. Protection of registers with “debug” privileges is described in Section 20.6.1 Protecting the Development Port Registers. This register is a fetch-only register. Using mtspr is ignored and using mfspr gives an undefined value. 6-18 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 150: Physical Location Of Special Registers

    For these registers, a bus cycle is performed on the internal bus with the following address. 0:17 18:22 23:27 28:31 0000 If any address error occurs on this cycle, an implementation-dependent software emulation interrupt is taken. MOTOROLA MPC823e REFERENCE MANUAL 6-19...
  • Page 151: Powerpc Standard Control Register Bit Assignment

    EE—External Interrupt Enable This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed. 6-20 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 152 1 = The interrupt prefix is 0xFFFn_nnnn. IR—Instruction Relocate This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed. MOTOROLA MPC823e REFERENCE MANUAL 6-21...
  • Page 153: The Condition Register

    • Bit 0—Negative (LT). The result is negative. • Bit 1—Positive (GT). The result is positive. • Bit 2—Zero (EQ). The result is zero. • Bit 3—Summary Overflow (SO). The values of this bit is copied from XER 6-22 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 154: Fixed-point Exception Cause Register

    Otherwise, it is cleared. Bits 3–24—Reserved These bits are reserved and must be set to 0. BCNT—Byte Count for Load/Store String Operations This field specifies the number of bytes to be transferred by a lswx or stswx instruction. MOTOROLA MPC823e REFERENCE MANUAL 6-23...
  • Page 155: Initializing The Control Registers

    The divide instructions have a relatively long latency, but those instructions can update the OV bit in the XER after one cycle. Therefore, data dependency on the XER is limited to one cycle, although the divide instruction latency can be a maximum of 11 clocks. 6-24 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 156: The Load/store Unit

    2-entry, 32-bit wide queue that holds fixed-point data. The load/store unit has a dedicated writeback bus so that loaded data received from the internal bus is written directly back to the fixed- or floating-point register files. MOTOROLA MPC823e REFERENCE MANUAL 6-25...
  • Page 157: Issuing Load/store Instructions

    Then, using a dedicated interface, the load/store unit notifies the integer unit of the need to calculate the effective address. All load/store instructions are executed and terminated in order. 6-26 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 158: Serializing Load/store Instructions

    When executing speculative load cycles to the nonspeculative external memory region, no external cycles are generated until the load instruction becomes nonspeculative. MOTOROLA MPC823e REFERENCE MANUAL 6-27...
  • Page 159: Executing Unaligned Instructions

    04’h 00’h 2 BUS CYCLES 04’h 00’h 2 BUS CYCLES 04’h 00’h 3 BUS CYCLES 04’h 00’h 3 BUS CYCLES 04’h Figure 6-7. Number of Bus Cycles Needed For Unaligned, Single Register Fixed-Point Load/Store Instructions 6-28 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 160: Little-endian Mode Support

    The MPC823e storage reservation supplies hooks for the support of storage reservation implementation in a hierarchical bus structure. For a full description of the storage reservation mechanism, refer to Section 7 PowerPC Architecture Compliance.
  • Page 161: Instruction Timing

    Location of Special Registers for detailed information. If the access terminates in a bus error, then an implementation-dependent software emulation interrupt is taken. All write operations to off-core special registers (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. 6-30 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 162: Storage Control Instructions

    Instruction Information Undefined Implementation Dependent Software Emulation Does Not Change Does Not Change Undefined Interrupt Floating-Point Unavailable Interrupt Does Not Change Does Not Change Undefined Program Interrupt Does Not Change Does Not Change Does Not Change MOTOROLA MPC823e REFERENCE MANUAL 6-31...
  • Page 163: Powerpc Architecture Compliance

    Illegal and reserved instruction class instructions are supported by implementation-dependent code and, thus the core hardware generates the implementation-dependent software emulation interrupt. How the core treats invalid and preferred instruction forms is described in the specific processor compliance sections. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 164: Exceptions

    • Move to/from system register instructions All hardware instructions are defined for the fixed-point processor in the PowerPC User Instruction Set Architecture (Book I) . For details about the performance of the various instructions, see Table 8-1 of this manual. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 165: Fixed-point Arithmetic Instructions

    In the cmpi , cmp , cmpli , and cmpl instructions, the L bit is applicable for 64-bit implementations. For the MPC823e, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0.
  • Page 166: Storage Synchronization Instructions

    The MPC823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx instructions is in the writethrough required mode.
  • Page 167: The Effect Of Operand Placement On Performance

    7.2.3 The Storage Control Instructions The MPC823e interprets the cache control instructions ( icbi , isync , dcbt , dcbi , dcbf , dcbz , dcbst , eieio , and dcbtst ) as if they pertain only to the MPC823e cache. These instructions do not broadcast.
  • Page 168: Timebase

    7.3.1 The Branch Processor 7.3.1.1 MACHINE STATE REGISTER. The floating-point exception mode is ignored by the MPC823e. The IP bit initial state after reset is set as programmed by the reset configuration specified in Section 12 System Interface Unit. 7.3.1.2 PROCESSOR VERSION REGISTER. The value of the PVR register’s version field is x’0050’.
  • Page 169: Reference And Change Bits

    • Supports fast software tablewalk mechanism 7.3.4 Reference and Change Bits No reference bit is supported by the MPC823e. However, the change bit is supported by using the data TLB error interrupt mechanism when writing to an unmodified page. 7.3.5 Storage Protection Two main protection modes are supported by the MPC823e: •...
  • Page 170: Processing

    01200 Implementation-Dependent Data TLB Miss 01300 Implementation-Dependent Instruction TLB Error 01400 Implementation-Dependent Data TLB Error 01500 - 01BFF Reserved 01C00 Implementation-Dependent Data Breakpoint 01D00 Implementation-Dependent Instruction Breakpoint 01E00 Implementation-Dependent Peripheral Breakpoint 01F00 Implementation-Dependent Nonmaskable Development Port MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 171: System Reset Interrupt

    (MSR =1) it is taken. If SRR1 Bit 30 =1, the interrupt is recoverable and the following registers are set. SRR0—Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 172: Data Storage Interrupt

    • The operand of a lwarx or stwcx is not word aligned. • The operand of a load/store individual scalar instruction is not naturally aligned when MSR = 1. • An attempt to execute a multiple/string instruction is made when MSR = 1. 7-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 173: Program Interrupt

    PowerPC Architecture Compliance 7.3.7.3.6 Program Interrupt. The MPC823e cannot generate a floating-point exception type interrupt. Likewise, an illegal instruction type program interrupt is not generated by the core, but an implementation-dependent software emulation interrupt is generated instead. A privileged instruction program interrupt is generated for an on-core valid special-purpose...
  • Page 174: Implementation-dependent Software Emulation Interrupt

    =1 and you try to fetch an instruction from a page whose effective page number cannot be translated by TLB. The following registers are set: SRR0–Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. 7-12 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 175: Implementation-specific Instruction Tlb Error Interrupt

    Set to 1 when Bit 4 is set. Otherwise, set to 0. 11–15 Set to 0. Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR MOTOROLA MPC823e REFERENCE MANUAL 7-13...
  • Page 176: Implementation-specific Data Tlb Miss Interrupt

    • An attempt was made to write to a page with a negated change bit. The following registers are set: SRR0—Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. 7-14 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 177: Implementation-specific Debug Register

    • When a peripheral breakpoint request is presented to the interrupt mechanism. • When the development port request is presented to the interrupt mechanism. Refer to Section 20 Development Capabilities and Interface for details on how to generate the development port request. MOTOROLA MPC823e REFERENCE MANUAL 7-15...
  • Page 178 The execution resumes from an address equal to the base indicated by the MSR and the following offset. • x’01D00’–For an instruction breakpoint match • x’01C00’–For a data breakpoint match • x’01E00’–For a development port maskable request or a peripheral breakpoint • x’01F00’–For a development port nonmaskable request 7-16 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 179: Partially Executed Instructions

    In the MPC823e, the instruction can be partially executed only in the case of load/store instructions that cause multiple access to the memory subsystem—multiple/string and unaligned load/store instructions.
  • Page 180: Instruction Execution Timing

    LDST Serialize + 1 Special Registers: mtspr, mttb, mttbu Move from External to the Core Load Latency LDST Special Registers: mfspr, mftb, mftbu Move from Special Registers — See List Located Internal to the Core: mfspr MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 181 Serialize + 1 Serialize + 1 LDST Yes (Before) Register (Debug, DAR, DSISR): mtspr, mfspr String Instructions: Serialize + 1 Serialize + 1 LDST lswi, lswx, stswi, stswx + Number + Number of Words of Words Accessed Accessed MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 182 Although a store (as well as mtspr for special registers external to the core) issued to the load/store unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until the bus is free. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 183: Instruction Execution Timing Examples

    This causes a bubble to occur in the instruction stream as shown in the execute line. Refer to Section 8.2.2.2 Private Writeback Bus Load for instances in which no such dependency exists. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 184: Writeback

    GCLK1 MULLI ADDIC FETCH MULLI ADDIC DECODE MULLI SUB, MULLI ADDIC READ + EXECUTE MULLI WRITEBACK Figure 8-3. Another Example of a Writeback Arbitration MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 185: Private Writeback Bus Load

    CACHE ADDRESS LOAD WRITEBACK E ADDRESS E DATA Figure 8-4. Example of a Private Writeback Bus Load The load and the xor writeback in the same clock since they use the writeback bus in two different ticks. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 186: Fastest External Load (data Cache Miss)

    Figure 8-5. Example of an External Load The sub instruction is dependent on the value read by the load. It causes three bubbles in the instruction execution stream. The external clock is shifted 90 ° relative to the internal clock. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 187: A Full History Buffer

    It takes one more bubble from the load writeback to allow further issue. This is the time for the history buffer to retire sub, add, and and. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 188: Branch Folding

    The issue of the branch itself is referred to as a bubble since no actual work is done by a branch. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 189: Branch Prediction

    The fetched instructions on the predicted path are not allowed to execute before the condition is finally resolved. Instead, they are stacked in the instruction prefetch queue. 8-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 190: Instruction Cache

    SECTION 9 INSTRUCTION CACHE The MPC823e instruction cache is a 16K four-way, set associative storage area. It is organized into 256 sets, four lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical code segments that need fast and deterministic execution time.
  • Page 191 • Tags and Data Arrays can be Accessed by the Core for Debugging and Testing Purposes • Special Support is Available when the MPC823e Processor is in Debug Mode. Refer to Section 9.9 Debug Support for More Information. MPC823e REFERENCE MANUAL...
  • Page 192 TAG254 W0 W1 W2 W3 SET255 TAG255 W0 W1 W2 W3 COMP COMP COMP COMP HIT1 HIT2 HIT3 HIT0 BIDIRECTIONAL MUX 4-> 1 TO LINE BUFFER/ FROM BURST BUFFER Figure 9-1. Instruction Cache Organization Block Diagram MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 193: Programming The Instruction Cache

    • Instruction cache address register (IC_ADR) • Instruction cache data port register (read-only) (IC_DAT) These registers are privileged and any attempt to access them while the core is in the problem state (MSR =1) results in a program interrupt. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 194: Instruction Cache Control And Status Register

    011 = LOAD & LOCK . 100 = UNLOCK LINE . 101 = UNLOCK ALL . 110 = INVALIDATE ALL . 111 = Reserved. Bits 7–9—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 195: Instruction Cache Address Register

    RESET — NOTE: — = Undefined. ADR—Address This field represents the address to be used in the command programmed in the CMD field of the IC_CST. The format may vary depending on the selected cache operation. MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 196: Instruction Cache Data Port Register

    When a cache hit occurs, bits 28-29 of the instruction address are used to select one word from the cache line whose tag matches the instruction pointer. The instruction is then immediately transferred to the instruction unit of the core. MOTOROLA MPC823e REFERENCE MANUAL...
  • Page 197: Instruction Cache Miss

    To minimize power consumption, the MPC823e instruction cache does not initiate a miss sequence in most cases when the instruction is inside a predicted path. The MPC823e instruction cache evaluates fetch requests to see if they are inside a predicted path and if a hit is detected, the requested data is delivered to the core.
  • Page 198: Invalidating The Instruction Cache

    MPC823e instruction cache. This instruction does not broadcast on the external bus and the MPC823e does not snoop this instruction if it is broadcasted by other masters. This command is not privileged and has no associated error cases. The instruction cache performs this instruction in one clock cycle.
  • Page 199: Loading And Locking The Instruction Cache

    This command has no error cases that you need to check. The instruction cache performs this instruction in one clock cycle. To accurately calculate the latency of this instruction, bus latency must be taken into consideration. 9-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 200: Unlocking The Entire Instruction Cache

    Instructions that originate in a cache-inhibited region and are stored in the burst buffer can be sent to the MPC823e core no more than once before being refetched. In the memory management unit, a memory region can be programmed as cache-inhibited. When...
  • Page 201: Instruction Cache Read

    Instruction Cache 9.4.6 Instruction Cache Read The MPC823e allows you to read all data stored in the instruction cache, including the content of the tags array. However, this operation is privileged and any attempt to perform it when the core is in the problem state (MSR =1) results in a program interrupt.
  • Page 202 These bits are reserved and must be set to 0. V—Valid Entry 0 = Entry is not valid. 1 = Entry is valid. L—Lock Entry 0 = Entry is unlocked. 1 = Entry is locked. MOTOROLA MPC823e REFERENCE MANUAL 9-13...
  • Page 203: Instruction Cache Write

    Bit 29—When set, way 1 is more recently used than way 0. 9.4.7 Instruction Cache Write Instruction cache write is only enabled when the MPC823e is in test mode. 9.5 RESTRICTIONS Zero wait state devices that are placed on the internal bus are considered to be in the cache-inhibited memory region and the hardware correct operation trusts the software to follow the exact steps mentioned in Section 9.7 Updating Code And Memory Region...
  • Page 204: Debug Support

    The MPC823e can be debugged either in debug mode or by a software monitor debugger. In both cases, the core of the MPC823e CPU asserts the internal freeze (FRZ) signal. When FRZ is asserted the instruction cache treats all misses as if they were from cache-inhibited regions and, assuming the debug routine is not in the instruction cache, the cache state remains exactly the same.
  • Page 205: Data Cache

    SECTION 10 DATA CACHE The MPC823e data cache is a 8K two-way, set-associative cache. It is organized into 256 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical data segments that need a fast and deterministic execution time.
  • Page 206: Organization Of The Data Cache

    TAG254 W0 W1 W2 W3 SET255 TAG255 W0 W1 W2 W3 TAG255 W0 W1 W2 W3 COMP COMP HIT1 HIT0 BIDIRECTIONAL MUX 2 -> 1 TO/FROM LINE BUFFER/ BURST BUFFER Figure 10-1. Data Cache Organization 10-2 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 207: Programming The Data Cache

    The following PowerPC instructions are supported by the data cache. 10.3.1.1 P PC USER INSTRUCTION SET ARCHITECTURE (BOOK I) OWER The data cache supports the sync instruction through a cache pipe clean indication to the core. MOTOROLA MPC823e REFERENCE MANUAL 10-3...
  • Page 208: Powerpc Virtual Environment Architecture (book Ii)

    OWER data cache supports the dcbi (data cache block invalidate) instruction. 10.3.2 Implementation-Specific Operations The MPC823e data cache includes some extended features in addition to those of the PowerPC architecture. The following are implementation-specific operations supported by the MPC823e: • Block lock •...
  • Page 209 1 = Address munging performed by the core is reversed before accessing the data cache, the instruction cache and storage. Byte swap is performed for the instruction and data caches’ external accesses. This bit is a read-only bit and any attempt to write to it is ignored. MOTOROLA MPC823e REFERENCE MANUAL 10-5...
  • Page 210 This field is sticky and set by the hardware. It is read-only and cleared when read. 0 = No Error. 1 = Error. Bits 13–31—Reserved These bits are reserved and must be set to 0. 10-6 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 211: Reading The Cache Structures

    10.3.3.3 READING THE CACHE STRUCTURES. To read the data stored in the data cache tags or registers, follow these steps: 1. Write to the DC_ADR. This register can also be read for debugging purposes. 2. Read the DC_DAT register. MOTOROLA MPC823e REFERENCE MANUAL 10-7...
  • Page 212 • 0 × 04—Copyback address register When reading from the DC_DAT register, the 20 bits of the tag (and related information) that is selected by the DC_ADR are placed in the targeted general-purpose register. The 10-8 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 213 1 = This entry is aged or least-recently used. D—Dirty or Clean Cache Line 0 = This entry has not been modified since it was read from memory. 1 = This entry has been modified since it was read from memory. MOTOROLA MPC823e REFERENCE MANUAL 10-9...
  • Page 214: Operating The Data Cache

    The cache operates in either writethrough or copyback mode, depending on how the memory management unit is programmed. If two logical blocks map to the same physical block, it is considered a programming error for them to specify different cache write policies. 10-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 215: Copyback Mode

    (the dirty line flush error is an imprecise interrupt). For more information about reading the address and data of a line, see Section 10.3.1.2 PowerPC Virtual Environment Architecture (Book II). MOTOROLA MPC823e REFERENCE MANUAL 10-11...
  • Page 216: Writethrough Mode

    10.4.4 Data Cache Freeze The MPC823e can be debugged either in debug mode or by a software monitor debugger. In both cases, the MPC823e core asserts the internal FRZ signal. For a detailed description of MPC823e debug support, refer to Section 20 Development Capabilities and Interface.
  • Page 217: Data Cache Coherency

    10.5 DATA CACHE COMMANDS 10.5.1 Flushing and Invalidating the Cache The MPC823e allows the data cache to be flushed and invalidated when it is being controlled by the software. The data cache can be invalidated by writing the UNLOCK ALL and INVALIDATE ALL commands to the DC_CST.
  • Page 218: Data Cache Instructions

    The MPC823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx. instructions is in the Write Through Required mode.
  • Page 219: Memory Management Unit

    SECTION 11 MEMORY MANAGEMENT UNIT The MPC823e implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. This implementation includes separate instruction and data memory management units. The MPC823e memory management unit is compliant with the PowerPC Microprocessor...
  • Page 220: Address Translation

    In the MPC823e, the table lookup and TLB reload are performed by a software routine with little hardware assistance. This partition simplifies the hardware and gives the system the opportunity to choose the translation table structure.
  • Page 221: Protection

    IMPLEMENTATION REAL PAGE NUMBER BYTE SPECIFIC NO ACCESS ERROR INTERRUPTS TO CORE PROTECTION TRANSLATION TRANSLATION LOOKUP ENABLED ENABLED TABLE EXCEPTION LOGIC 32-BIT REAL ADDRESS Figure 11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages MOTOROLA MPC823e REFERENCE MANUAL 11-3...
  • Page 222: Storage Control

    Control Register and Section 11.6.1.2 MMU Data Control Register for details. The MPC823e does not generate an exception for a reference bit update because there is no entry for a reference bit in the translation lookaside buffer. The change bit updates are implemented by the software, but the hardware treats the change bit as a write-protect attribute.
  • Page 223: Translation Table Structure

    Memory Management Unit 11.5 TRANSLATION TABLE STRUCTURE The MPC823e memory management unit includes special hardware to assist in a two-level software tablewalk. Other table structures are not precluded. Figure 11-2 and Figure 11-3 illustrate the two levels of translation table structures supported by MPC823e special hardware.
  • Page 224 20 - FOR 4K LEVEL TWO DESCRIPTOR 1023 18 - FOR 16K 13 - FOR 512K 9 - FOR 8M REAL PAGE ADDRESS PAGE OFFSET REAL ADDRESS Figure 11-2. Two Level Translation Table When MD_CTR(TWAM) = 1 11-6 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 225 LEVEL TWO DESCRIPTOR 1023 20 - FOR 4K 18 - FOR 16K 13 - FOR 512K 9 - FOR 8M REAL PAGE ADDRESS PAGE OFFSET REAL ADDRESS Figure 11-3. Two Level Translation Table When MD_CTR(TWAM) = 0 MOTOROLA MPC823e REFERENCE MANUAL 11-7...
  • Page 226 Table 11-2. Number of Identical Entries Required in the Level One Table PAGE SIZE MD_CTR MD_CTR TWAM TWAM — 512K Table 11-3. Number of Identical Entries Required in the Level Two Table PAGE SIZE MD_CTR MD_CTR TWAM TWAM — 512K 1,024 1,024 11-8 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 227: Level One Descriptor

    PS—Page Size Level One 00 = Small (4K or 16K). 01 = 512K. 11 = 8M. 10 = Reserved. WT—Writethrough Attribute for Entry 0 = Copyback cache policy region (default). 1 = Writethrough cache policy region. MOTOROLA MPC823e REFERENCE MANUAL 11-9...
  • Page 228: Level Two Descriptor

    INSTRUCTION PAGES DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE PRIVILEGED MODE PROBLEM MODE No access No access No access No access Executable No access Read/Write No access Executable Executable Read/Write Read-only Executable Executable Read/Write Read/Write 11-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 229 INSTRUCTION PAGES DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE PRIVILEGED MODE PROBLEM MODE No access No access No access No access Executable No access Read/Write No access Executable Executable Read/Write Read-only Executable Executable Read/Write Read/Write MOTOROLA MPC823e REFERENCE MANUAL 11-11...
  • Page 230 Executable Read/Write Read-only Executable Executable Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: Mx_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid 11-12 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 231 Executable Read/Write Read-only Executable Executable Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: Mx_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-13...
  • Page 232 This bit is the cache-inhibit attribute for the entry. Setting this bit will inhibit cache fill for accesses to this page. V—Valid This is the page valid bit. Setting this bit indicates the page is valid or resident in the memory (for demand page memory management). 11-14 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 233: Programming The Memory Management Unit

    Instruction MMU Debug CAM MD_DCAM Data MMU Debug CAM MI_DRAM0 Instruction MMU Debug RAM0 MD_DRAM0 Data MMU Debug RAM0 Instruction MMU Debug RAM1 Data MMU Debug RAM1 MI_DRAM1 MD_DRAM1 Figure 11-4. Organization of the Memory Management Unit Registers MOTOROLA MPC823e REFERENCE MANUAL 11-15...
  • Page 234: Control Registers

    0 = Ignore problem/privilege state during address compare. 1 = Consider problem/privilege state according to MI_RPN[24:27]. Bits 7–18—Reserved These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read. 11-16 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 235: Mmu Data Control Register

    This bit is the data cache attributes default value when the data MMU is disabled (MSR = 0). RSV4D—Reserve Four Data TLB Entries 0 = DTLB_INDX decremented modulo 32. 1 = DTLB_INDX decremented modulo 28. MOTOROLA MPC823e REFERENCE MANUAL 11-17...
  • Page 236: Mmu Current Address Space Id Register

    Bits 0–27—Reserved These bits are reserved and must be set to 0. Ignored on a write. CASID—Current Address Space ID This field is compared to the ASID field of a TLB entry to qualify a match. 11-18 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 237: Mmu Instruction Effective Page Number Register

    0 = The TLB entry is invalid. 1 = The TLB entry is valid. ASID—Address Space ID This field represent the address space ID of the instruction TLB entry to be compared with the CASID field of the M_CASID register. MOTOROLA MPC823e REFERENCE MANUAL 11-19...
  • Page 238: Mmu Data Effective Page Number Register

    These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read. ASID—Address Space ID This field is the address space IDs of the TLB entry to be compared with the CASID field of the M_CASID register. 11-20 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 239: Mmu Instruction Real Page Number Register

    PP2 field, the same protection code has different protection schemes. 4K PAGES WITH 1K RESOLUTION PROTECTION INSTRUCTION PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Executable No access Executable Executable Executable Executable MOTOROLA MPC823e REFERENCE MANUAL 11-21...
  • Page 240 This field contains a protection code for the second subpage in a 4K page. Depending on the encoding mode, this field has different meanings. 4K PAGES WITH 1K RESOLUTION PROTECTION INSTRUCTION PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Executable No access Executable Executable Executable Executable 11-22 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 241 Executable No access Executable Executable Executable Executable PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MI_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-23...
  • Page 242 Executable No access Executable Executable Executable Executable PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MI_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid 11-24 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 243 0 = This entry matches only if the ASID filed in the TLB entry matches the value of the M_CASID register. 1 = ASID comparison is disabled for the entry. CI—Cache Inhibit This bit is the cache-inhibit attribute for the TLB entry. V—Valid This bit indicates that a TLB entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-25...
  • Page 244: Mmu Data Real Page Number Register

    PP2 field, the same protection code has different protection schemes. 4K PAGES WITH 1K RESOLUTION PROTECTION DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Read/Write No access Read/Write Read-only Read/Write Read/Write 11-26 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 245 This field contains a protection code for the second subpage in a 4K page. Depending on the encoding mode, this field has different meanings. 4K PAGES WITH 1K RESOLUTION PROTECTION DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Read/Write No access Read/Write Read-only Read/Write Read/Write MOTOROLA MPC823e REFERENCE MANUAL 11-27...
  • Page 246 Read/Write No access Read/Write Read-only Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MD_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid 11-28 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 247 Read/Write No access Read/Write Read-only Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MD_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-29...
  • Page 248 0 = This entry matches only if the ASID filed in the TLB entry matches the value of the M_CASID register. 1 = ASID comparison is disabled for a TLB entry. CI—Cache Inhibit This bit is the cache-inhibit attribute for a TLB entry. V—Valid This bit indicates that a TLB entry is valid. 11-30 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 249: Mmu Instruction Access Protection Register

    (Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for 32-Bit Microprocessors manual: 00 = All accesses are considered privileged. 01 = Access permission defined by page protection bits. 10 = Problem and privileged interpretation is swapped. 11 = All accesses are considered problem. MOTOROLA MPC823e REFERENCE MANUAL 11-31...
  • Page 250: Mmu Data Access Protection Register

    (Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for 32-Bit Microprocessors manual: 00 = All accesses are considered privileged. 01 = Access permission defined by page protection bits. 10 = Problem and privileged interpretation is swapped. 11 = All accesses are considered problem. 11-32 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 251: Mmu Instruction Tablewalk Control Register

    0 = Unguarded storage. 1 = Guarded storage. PS—Page Size Level One Default value on instruction TLB miss is 00. 00 = Small (4K or 16K). 01 = 512K. 11 = 8M. 10 = Reserved. MOTOROLA MPC823e REFERENCE MANUAL 11-33...
  • Page 252: Mmu Data Tablewalk Control Register

    MD_EPN[12:21] when MD_CTR = 0. TWAM G—Guarded When written, this bit of the entry has the following settings and is set to 0 on a data TLB miss: 0 = Unguarded storage. 1 = Guarded storage. 11-34 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 253 When written, this bit has the following settings and is set to 1 on a data TLB miss. When this bit is read, it returns a zero. 0 = Entry is invalid. 1 = Entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-35...
  • Page 254: Mmu Tablewalk Base Register

    This field is ignored on write. It returns MD_EPN[0:9] on read when MD_CTR = 1 and TWAM MD_EPN[2:11] when MD_CTR = 0. TWAM Bits 30–31—Reserved These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read. 11-36 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 255: Mmu Tablewalk Special Register

    The values of the MD_CAM, MD_RAM0, and MD_RAM1 registers can be read using the mfspr instruction. If you try to write to the MD_RAM0 and MD_RAM1 registers using the mtspr instruction, it will be considered a NOP (no operation) instruction. MOTOROLA MPC823e REFERENCE MANUAL 11-37...
  • Page 256: Mmu Data Cam Entry Read Register

    0 = Subpage 2 (address[20:21] = 10) is not valid. 1 = Subpage 2 (address[20:21] = 10) is valid. For Bit 23: 0 = Subpage 3 (address[20:21] = 11) is not valid. 1 = Subpage 3 (address[20:21] = 11) is valid. 11-38 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 257: Mmu Data Ram Entry Read Register 0

    — ADDR SPR 825 FIELD APGI RESERVED RESET — — — — — — ADDR SPR 825 NOTE: — = Undefined. RPN—Real Page Number These bits are the most-significant bits of the page’s physical address. MOTOROLA MPC823e REFERENCE MANUAL 11-39...
  • Page 258 0 = Copyback data cache policy page entry. 1 = Writethrough data cache policy page entry. CI—Cache-Inhibit When this bit is 0, it is not cache-inhibited. Bits 30–31—Reserved These bits are reserved and must be set to 0. 11-40 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 259: Mmu Data Ram Entry Read Register 1

    MMU interrupt invocation. Software must take an appropriate action before setting this bit to 1. 1 = Changed region. Write access is allowed to this page. EVF—Entry Valid Flag 0 = Entry is invalid. 1 = Entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-41...
  • Page 260 1 = Subpage 2 (address[20:21]=10) problem write access is permitted. URP3—Problem (User) Read Permission Page Three 0 = Subpage 3 (address[20:21]=11) problem read access is not permitted. 1 = Subpage 3 (address[20:21]=11) problem read access is permitted. 11-42 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 261: Mmu Instruction Content-addressable Registers

    FIELD RESET — ADDR SPR 816 FIELD ASID RESET — — — — — ADDR SPR 816 NOTE: — = Undefined. EPN—Effective Page Number These bits are the most-significant bits of the page’s effective address. MOTOROLA MPC823e REFERENCE MANUAL 11-43...
  • Page 262 1 = Subpage 1 (address[20:21]=01) is valid. Bit 30: 0 = Subpage 2 (address[20:21]=10) is not valid. 1 = Subpage 2 (address[20:21]=10) is valid. Bit 31: 0 = Subpage 3 (address[20:21]=11) is not valid. 1 = Subpage 3 (address[20:21]=11) is valid. 11-44 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 263: Mmu Instruction Ram Entry Read Register 0

    100 = Reserved. 101 = Reserved. 110 = Reserved. CI—Cache-Inhibit When this bit is 0, it is not cache-inhibited. APG—Access Protection Group A maximum of 16 protection groups are supported and represented in one’s compliment format. MOTOROLA MPC823e REFERENCE MANUAL 11-45...
  • Page 264: Mmu Instruction Ram Entry Read Register 1

    MI_CAM register. MI_RAM1 FIELD RESERVED RESET ADDR SPR 818 FIELD RESERVED RESET — — — ADDR SPR 818 NOTE: — = Undefined. Bits 0–25—Reserved These bits are reserved and must be set to zero. 11-46 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 265: Interrupts

    The software tablewalk code is responsible for loading the translation information of the missed page from the translation table that resides in the memory. Refer to Section 11.8.1.1 Translation Reload Examples for more information. MOTOROLA MPC823e REFERENCE MANUAL 11-47...
  • Page 266: Implementation-specific Instruction Tlb Error

    The data storage interrupt status register indicates the cause of the data TLB error interrupt. For bit assignments refer to Section 7.3.7.3.14 Implementation-Specific Data TLB Error Interrupt. It is the software’s responsibility to invoke the data storage interrupt handler. 11-48 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 267: Manipulating The Translation Lookaside Buffer

    • Performs a write to the TLB entry by loading the tablewalk level two entry value to the MI_RPN or MD_RPN register. • A special register (M_TW) is available for the software tablewalk routine, in addition to the PowerPC architecture’s special registers (SPRG0–SPRG3). Using this register allows for more efficient interrupt handling. MOTOROLA MPC823e REFERENCE MANUAL 11-49...
  • Page 268: Translation Reload Examples

    # load R1 with level two pointer # while taking into account the # page size R1, (R1) # Load level two page entry mtspr MI_RPN, R1 # Write TLB entry mfspr R1, M_TW # restore R1 11-50 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 269: Controlling The Tlb Replacement Counter

    TLB reload. 11.8.3 Invalidating the Translation Lookaside Buffer The MPC823e implements the tlbie instruction to invalidate the TLB entries. This instruction invalidates TLB entries in the translation lookaside buffer that hits, including the reserved entries. Notice that with 4K page size, the 22 most-significant bits of the effective address are used in the comparison because no segment registers are implemented.
  • Page 270: Requirements For Accessing The Memory Management Unit Control Registers

    All instruction and data memory management unit control registers must be accessed when instruction and data address translation is turned off. Prior to an mtspr MD_DBCAM receive instruction, an eieio instruction must be placed and executed before you write to the Mx_CAM register. 11-52 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 271: System Interface Unit

    The external bus interface handles the transfer of information between internal buses and the memory or peripherals in the external address space. The MPC823e is designed to allow external bus masters to request and obtain mastership of the system bus. For additional information on bus operation, see Section 13 External Bus Interface .
  • Page 272: Features

    PCMCIA socket with a maximum of eight memory or I/O windows. Note: Both the MPC823e and MPC821 have the same PCMCIA module except that the MPC823e has only one valid slot (Slot B). Programming a window to be assigned to Slot A may cause an erroneous operation.
  • Page 273 (RTCAL) register. The real-time clock is clocked by the PITRTCLK clock. • Freeze Support —The system interface unit determines whether the software watchdog timer, periodic interrupt timer, timebase, decrementer, and real-time clock will continue to run in freeze mode. MOTOROLA MPC823e REFERENCE MANUAL 12-3...
  • Page 274 Figure 12-1 illustrates a block diagram of the system configuration and protection logic. MODULE CONFIGURATION MONITOR PERIODIC INTERRUPT INTERRUPT TIMER SOFTWARE INTERRUPT OR WATCHDOG TIMER SYSTEM RESET POWERPC CLOCK INTERRUPT DECREMENTER POWERPC INTERRUPT TIMEBASE COUNTER REAL-TIME INTERRUPT CLOCK Figure 12-1. System Configuration and Protection Logic 12-4 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 275: Interrupt Configuration

    System Interface Unit 12.3 INTERRUPT CONFIGURATION Many aspects of MPC823e system configuration are controlled by the SIU module configuration register (SIUMCR). The SIUMCR primarily controls the external bus arbitration logic, external master support, and pin multiplexing. See Section 12.12.1.1 SIU Module Configuration Register for more information.
  • Page 276: Priority Of The Interrupt Sources

    00001100 IRQ2 00010000 Level 2 00010100 IRQ3 00011000 Level 3 00011100 IRQ4 00100000 Level 4 00100100 IRQ5 00101000 Level 5 00101100 IRQ6 00110000 Level 6 00110100 IRQ7 00111000 Lowest Level 7 00111100 16-31 Reserved — 12-6 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 277: Programming The Interrupt Controller

    When set, this field indicates a pending internal level interrupt of a corresponding value. See Figure 12-2 for more information. 0 = The appropriate interrupt is not pending. 1 = The appropriate interrupt is pending. MOTOROLA MPC823e REFERENCE MANUAL 12-7...
  • Page 278: Siu Interrupt Mask Register

    IRQx interrupt is falling edge-triggered or low logical level triggered. The WMx field in the SIEL register determines if the corresponding IRQx interrupt will cause the MPC823e to exit low-power mode. Note: IRQ0 will generate a non-maskable interrupt even if its corresponding IRM0 bit is not set.
  • Page 279: Siu Interrupt Edge/level Register

    When the EDx bit is 0, a low logical level in the IRQx signal is an interrupt request. The WMx bit, if set, indicates that a low level detection in the corresponding interrupt request line causes the MPC823e to exit low-power mode. SIEL...
  • Page 280: Siu Interrupt Vector Register

    INTC—Interrupt Code This field indicates the highest priority pending interrupt. Bits 8–31—Reserved These bits are reserved and must be set to 0. The value equals the interrupt number multiplied by four. See Table 12-1 for details. 12-10 MPC823e REFERENCE MANUAL MOTOROLA...
  • Page 281: The Bus Monitor

    The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The MPC823e system interface unit provides a bus monitor option that monitors internally generated external bus accesses on the external bus. At the start of the transfer start (TS) signal, the monitor begins counting and stops when the transfer acknowledge (TA) or transfer error (TEA) signal is asserted.
  • Page 282: The Powerpc Decrementer

    This binary counter is clocked by the same frequency as the timebase. In the MPC823e, the decrementer is clocked by the TMBCLK clock, so you must enable the TBE bit in the TBSCR for the decrementer to start.
  • Page 283: Decrementer Register

    FIELD RESET — NOTE: — = Undefined. DEC—Decrementer This field is used by a down counter to cause decrementer interrupts. A read of this register always returns the current count value from the down counter. MOTOROLA MPC823e REFERENCE MANUAL 12-13...
  • Page 284: The Powerpc Timebase

    There is no interrupt or other indication generated when the count rolls over. The period of the timebase depends on the driving frequency. For the MPC823e, the timebase is clocked by the TMBCLK clock and the period for the timebase is:...
  • Page 285: Timebase Reference Registers

    (IMMR & 0xFFFF0000) + 0x204 FIELD TBREFU RESET — ADDR (IMMR & 0xFFFF0000) + 0x206 NOTE: — = Undefined. TBREFU—Timebase Reference Upper These bits represent the 32-bit reference value for the upper part of the timebase. MOTOROLA MPC823e REFERENCE MANUAL 12-15...
  • Page 286: Timebase Status And Control Register

    If set, these bits indicate that a match has been detected between the corresponding reference register (TBREFU for REFA and TBREFL for REFB) and the timebase low register. Each bit must be cleared by writing a 1. 12-16 MPC823e REFERENCE MANUAL MOTOROLA...