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Table of Contents

Summary of Contents for Motorola MPC823e

Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Page 2 All other trademarks are the property of their respective owners. Acknowledgments The MPC823e Support Team would like to thank the following people for their contribution to the success of the MPC823e: Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,...
Page 3: Table Of Contents
The LCD Controller ............1-10 The PCMCIA-ATA Controller ..............1-10 Power Management ................1-11 System Debug Support ...............1-11 Applications ..................1-11 Differences Between MPC823 (Rev B) and MPC823e .......1-12 MPC823e Glueless System Design ............1-12 Section 2 External Signals The System Bus Signals ...............2-2 Section 3...
Page 4 Power Switching Example ..........5-26 5.4.2.2 Register Lock ..............5-27 Low-Power Operation ................. 5-28 Section 6 The PowerPC Core Features ....................6-1 Basic Structure of the Core ..............6-2 6.2.1 Instruction Flow Within the Core ..........6-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 5 Atomic Update Primitives ............6-29 6.6.9 Instruction Timing ..............6-30 6.6.10 Stalling Storage Control Instructions ........6-30 6.6.11 Accessing Off-Core Special Registers ........6-30 6.6.12 Storage Control Instructions .............6-31 6.6.13 Exceptions ................6-31 6.6.13.1 DAR, DSISR, and BAR Operation ........6-31 Section 7 MOTOROLA MPC823e REFERENCE MANUAL...
Page 6 Unsupported Registers ........... 7-6 7.3.2.2 Added Registers ............. 7-6 7.3.3 Storage Model ................7-6 7.3.3.1 Address Translation ............7-6 7.3.4 Reference and Change Bits ............7-7 7.3.5 Storage Protection ..............7-7 7.3.6 Storage Control Instructions ............7-7 MPC823e REFERENCE MANUAL MOTOROLA...
Page 7 Instruction Execution Timing Instruction Timing List ................8-1 Instruction Execution Timing Examples ..........8-4 8.2.1 Data Cache Load ...............8-4 8.2.2 Writeback ...................8-5 8.2.2.1 Writeback Arbitration ............8-5 8.2.2.2 Private Writeback Bus Load ...........8-6 8.2.3 Fastest External Load (Data Cache Miss) ........8-7 MOTOROLA MPC823e REFERENCE MANUAL...
Page 8 Programming the Data Cache ............10-3 10.3.1 PowerPC Architecture Instructions .......... 10-3 10.3.1.1 PowerPC User Instruction Set Architecture (Book I) ..10-3 10.3.1.2 PowerPC Virtual Environment Architecture (Book II) ..10-4 10.3.1.3 PowerPC Operating Environment Architecture (Book III) ............... 10-4 MPC823e REFERENCE MANUAL MOTOROLA...
Page 9 MMU Data Control Register ........11-17 11.6.1.3 MMU Current Address Space ID Register ....11-18 11.6.1.4 MMU Instruction Effective Page Number Register ..11-19 11.6.1.5 MMU Data Effective Page Number Register ....11-20 11.6.1.6 MMU Instruction Real Page Number Register ....11-21 MOTOROLA MPC823e REFERENCE MANUAL...
Page 10 12.3.3 Programming the Interrupt Controller ........12-7 12.3.3.1 SIU Interrupt Pending Register ........12-7 12.3.3.2 SIU Interrupt Mask Register ......... 12-8 12.3.3.3 SIU Interrupt Edge/Level Register ........ 12-9 12.3.3.4 SIU Interrupt Vector Register ........12-10 viii MPC823e REFERENCE MANUAL MOTOROLA...
Page 11 Bus Signal Descriptions ..............13-4 13.4 Bus Interface Operation ..............13-7 13.4.1 Basic Transfers ................13-8 13.4.2 Single Beat Transfers ...............13-8 13.4.2.1 Single Beat Read Flow ..........13-9 13.4.2.2 Single Beat Write Flow ..........13-12 13.4.3 Burst Transfers ...............13-16 13.4.4 The Burst Mechanism ............13-16 MOTOROLA MPC823e REFERENCE MANUAL...
Page 12 14.4 Setting the Endian Mode Of Operation ..........14-5 Section 15 Memory Controller 15.1 Features ....................15-1 15.2 Architecture ..................15-4 15.3 Register Model ..................15-7 15.3.1 Register Descriptions ............... 15-9 15.3.1.1 Base Registers ............. 15-9 MPC823e REFERENCE MANUAL MOTOROLA...
Page 13 Control ............15-65 15.5.4.2.9 Disable Timer Mechanism ......15-65 15.5.4.2.10 Last Word ............15-65 15.5.5 The Wait Mechanism ..............15-66 15.5.5.1 Internal and External Synchronous Master ....15-66 15.5.5.2 External Asynchronous Master ........15-67 15.5.5.3 Handling Variable Access Time and Slow Devices ..15-68 MOTOROLA MPC823e REFERENCE MANUAL...
Page 14 16.2.6.9 RISC Timer Table Algorithm ........16-25 16.2.6.10 Using the Timers to Track Microcontroller Loading ..16-25 16.3 Digital Signal Processing ..............16-26 16.3.1 Features ................. 16-26 16.3.2 DSP Operation ............... 16-26 16.3.2.1 Hardware ..............16-27 MPC823e REFERENCE MANUAL MOTOROLA...
Page 15 Application Example ........16-53 16.3.4.5 FIR6–Complex C, Real X, and Complex Y ....16-54 16.3.4.5.1 Coefficients and Sample Data Buffers ...16-54 16.3.4.5.2 FIR6 Function Descriptor .......16-55 16.3.4.5.3 FIR6 Parameter Packet ........16-57 16.3.4.6 IIR–Real C, Real X, Real Y .........16-57 MOTOROLA MPC823e REFERENCE MANUAL xiii...
Page 16 Timers ....................16-75 16.4.1 Features ................. 16-75 16.4.2 Timer Operation ..............16-76 16.4.2.1 Cascaded Mode ............16-77 16.4.2.2 Timer Global Configuration Register ......16-78 16.4.2.3 Timer Mode Registers ..........16-79 16.4.2.4 Timer Reference Registers ......... 16-80 MPC823e REFERENCE MANUAL MOTOROLA...
Page 17 The Serial Interface with Time-Slot Assigner ........16-113 16.7.1 Features ................16-115 16.7.2 Configuring the Time-Slot Assigner ........16-115 16.7.3 Enabling Connections to the Time-Slot Assigner ....16-118 16.7.4 Serial Interface RAM Operation ...........16-118 16.7.4.1 One Multiplexed Channel with Static Frames ...16-119 MOTOROLA MPC823e REFERENCE MANUAL...
Page 18 16.9.7 SCCx Parameter RAM Memory Map ........16-184 16.9.8 Handling Interrupts In the SCCs .......... 16-189 16.9.8.1 Interrupt Handling in the SCC Event Register ..16-189 16.9.8.2 Interrupt Handling in the SCC Mask Register ... 16-189 MPC823e REFERENCE MANUAL MOTOROLA...
Page 19 16.9.15.20 SCCx UART Status Register ........16-233 16.9.15.21 SCC2 UART Programming Example ......16-233 16.9.15.22 S-Record Programming Example ......16-235 16.9.16 The SCCs In HDLC Mode ............16-236 16.9.16.1 Features ..............16-237 16.9.16.2 SCCx HDLC Channel Frame Transmission Process ..............16-237 MOTOROLA MPC823e REFERENCE MANUAL xvii...
Page 20 Exceptions to RFC 1549 ........... 16-273 16.9.19.7 SCCx ASYNC HDLC Implementation ...... 16-273 16.9.19.8 SCCx ASYNC HDLC Parameter RAM Memory Map ............. 16-274 16.9.19.9 Configuring the SCCx ASYNC HDLC Parameters ..16-276 16.9.19.10 SCCx ASYNC HDLC Commands ......16-277 xviii MPC823e REFERENCE MANUAL MOTOROLA...
Page 21 SCCx Transparent Parameter RAM Memory Map ..16-307 16.9.21.6 SCCx Transparent Commands .........16-307 16.9.21.7 SCCx Transparent Controller Errors ......16-309 16.9.21.8 SCCx Transparent Mode Register ......16-309 16.9.21.9 SCCx Transparent Receive Buffer Descriptor ..16-310 16.9.21.10 SCCx Transparent Transmit Buffer Descriptor ..16-312 MOTOROLA MPC823e REFERENCE MANUAL...
Page 22 Features ..............16-319 16.9.22.2 Ethernet On the MPC823e ........16-320 16.9.22.3 Understanding Ethernet on the MPC823e ....16-321 16.9.22.4 Connecting the MPC823e to the EEST ....16-321 16.9.22.5 SCCx Ethernet Channel Frame Transmission Process ..............16-323 16.9.22.6 SCCx Ethernet Channel Frame Reception Process ..............
Page 23 Sending a Preamble ..........16-397 16.11.6.9 SMCx UART Controller Errors ........16-397 16.11.6.10 SMCx UART Mode Register ........16-398 16.11.6.11 SMCx UART Receive Buffer Descriptor ....16-399 16.11.6.12 SMCx UART Transmit Buffer Descriptor ....16-403 16.11.6.13 SMCx UART Event Register ........16-405 MOTOROLA MPC823e REFERENCE MANUAL...
Page 24 SMCx GCI Mask Register ........16-433 16.12 The Serial Peripheral Interface ............16-433 16.12.1 Features ................16-434 16.12.2 SPI Clocking and Pin Functions ........... 16-435 16.12.3 The SPI Transmission and Reception Process ....16-436 16.12.3.1 MultiMaster Operation ..........16-437 xxii MPC823e REFERENCE MANUAL MOTOROLA...
Page 25 C Event Register ............16-475 16.13.7.8 C Mask Register .............16-476 16.13.8 C Controller Initialization Sequence ........16-476 16.14 The Parallel I/O Ports ..............16-477 16.14.1 Features ................16-478 16.14.2 Port A Pin Functionality ............16-478 16.14.3 The Port A Registers ............16-480 MOTOROLA MPC823e REFERENCE MANUAL xxiii...
Page 26 CPM Interrupt Mask Register ........16-509 16.15.5.4 CPM Interrupt In-Service Register ......16-510 16.15.5.5 CPM Interrupt Vector Register ......... 16-511 16.15.6 Interrupt Handling Examples ..........16-511 16.15.6.1 PC6 Interrupt Handler Example ........ 16-511 16.15.6.2 USB Interrupt Handler Example ....... 16-512 xxiv MPC823e REFERENCE MANUAL MOTOROLA...
Page 27 Types of LCD Interfaces ............18-3 18.1.2.1 Passive LCD Interface ..........18-4 18.1.2.2 Active LCD Interface .............18-5 18.1.2.3 Smart Panel LCD Interface ...........18-5 18.2 The MPC823e LCD Controller ............18-6 18.3 LCD Controller Operation ..............18-8 18.3.1 FIFO Control ................18-9 18.3.2 Pixel Generation ..............18-10 18.3.2.1 Grayscale ..............18-10...
Page 28 Video Controller Configuration Register ........19-5 19.3.2 Video Status Register .............. 19-7 19.3.3 Video Command Register ............19-8 19.3.4 Video Background Color Buffer Register ......... 19-9 19.3.5 Video Frame Configuration Register (Set 0) ......19-10 xxvi MPC823e REFERENCE MANUAL MOTOROLA...
Page 29 20.3.1 Internal Watchpoints and Breakpoints ........20-9 20.3.1.1 Restrictions ..............20-12 20.3.1.2 Byte And Half-Word Working Modes ......20-12 20.3.1.3 Context-Dependent Filter ..........20-14 20.3.1.4 Ignore First Match Option ...........20-15 20.3.1.5 Generating Compare Types ........20-15 20.3.2 Basic Operation ..............20-16 MOTOROLA MPC823e REFERENCE MANUAL xxvii...
Page 30 Load/Store Support Comparators Control Register..20-48 20.6.2.7 Load/Store Support AND-OR Control Register ..20-50 20.6.2.8 Breakpoint Counter A Value and Control Register ..20-53 20.6.2.9 Breakpoint Counter B Value and Control Register ..20-54 20.6.3 Debug Mode Registers ............20-55 xxviii MPC823e REFERENCE MANUAL MOTOROLA...
Page 31 The sample/preload Instruction ..........21-20 21.3.3 The bypass Instruction ............21-20 21.3.4 The clamp Instruction .............21-20 21.3.5 The hi-z Instruction ..............21-20 21.4 MPC823e Restrictions ..............21-21 Section 22 DC Electrical Specifications 22.1 Maximum Ratings (GND = 0V) ............22-1 22.2 Thermal Characteristics ..............22-2 22.3 Power Considerations .................22-2...
Page 32 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Example #3 ...................A-4 Appendix B MPC823e Instruction Set Instruction Formats ................B-1 Split-Field Notation ................B-1 Instruction Fields ...................B-2 Notations and Conventions ..............B-3 The MPC823e Instruction Set ...............B-6 MPC823e REFERENCE MANUAL MOTOROLA...
Page 33 5-11. BRGCLK Divider ....................5-19 5-12. SYNCCLK Divider ..................5-20 5-13. LCDCLK Divider .....................5-21 5-14. LCD Clock Timing Diagram ................5-21 5-15. MPC823e Power Rails and TEXP Status ............5-24 5-16. External Power Supply Scheme ..............5-26 5-17. Register Lock Mechanism ................5-28 MOTOROLA MPC823e REFERENCE MANUAL...
Page 34 LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 5-18. MPC823e Low-Power Mode Flowchart ............5-29 Section 6 The PowerPC Core 6-1. Block Diagram of the Core ................6-3 6-2. Instruction Flow Conceptual Diagram .............. 6-3 6-3. Basic Instruction Pipeline Timing Diagram ............6-4 6-4.
Page 35 11-4. Organization of the Memory Management Unit Registers ......11-15 Section 12 System Interface Unit 12-1. System Configuration and Protection Logic ...........12-4 12-2. MPC823e Interrupt Structure .................12-5 12-3. Interrupt Table Handling Example ..............12-11 12-4. Real-Time Clock Block Diagram ..............12-17 12-5. Periodic Interrupt Timer Block Diagram ............12-22 12-6.
Page 36 15-11. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 10 or 11, SCY = 0, CSNT = 1, and TRLX = 1) ............15-33 15-12. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 00, SCY = 0, CSNT = 1, and TRLX = 1) ................15-34 15-13.
Page 37 15-54. EDO DRAM Burst Read Access ..............15-92 15-55. EDO DRAM Burst Write Access ..............15-93 15-56. EDO DRAM Refresh Cycle (CAS Before RAS) ...........15-94 15-57. EDO DRAM Exception Cycle ...............15-95 15-58. Blank Worksheet for a UPM .................15-96 MOTOROLA MPC823e REFERENCE MANUAL xxxv...
Page 38 16-36. SDMA Data Paths ..................16-83 16-37. SDMA Bus Arbitration .................. 16-84 16-38. IDMA Buffer Descriptor Ring ................ 16-91 16-39. Single-Address, Peripheral Write, Asynchronous TA ........ 16-103 16-40. Single-Address, Peripheral Write, Synchronous TA ........16-104 xxxvi MPC823e REFERENCE MANUAL MOTOROLA...
Page 39 16-76. SCC2 UART Receive Buffer Descriptor Example ........16-221 16-77. SCCx UART Interrupt Event Example ............16-227 16-78. SCCx HDLC Framing Structure ..............16-234 16-79. HDLC Address Recognition Example ............16-238 16-80. SCC2 HDLC Receive Buffer Descriptor Example ........16-245 16-81. HDLC Interrupt Event Example ..............16-251 MOTOROLA MPC823e REFERENCE MANUAL xxxvii...
Page 40 16-87. Delayed RTSx Mode .................. 16-263 16-88. HDLC Bus Time-Slot Assigner Transmission Line Configuration ....16-263 16-89. LocalTalk Frame Format ................16-265 16-90. Connecting the MPC823e to AppleTalk ............. 16-267 16-91. ASYNC HDLC Frame Structure ..............16-270 16-92. Reception Flowchart .................. 16-272 16-93.
Page 41 16-131.Byte Read from Device without Internal Addresses ........16-460 16-132.I C Memory Format ...................16-467 16-133.Parallel Block Diagram For PA15 ..............16-482 16-134.Parallel Block Diagram For PA14 ..............16-483 16-135.MPC823e Interrupt Structure ..............16-499 16-136.Interrupt Request Masking ................16-504 Section 17 PCMCIA Interface 17-1. System with One PCMCIA Socket ..............17-2 17-2.
Page 42 18-2. LCD Subsystem ..................... 18-3 18-3. Passive Interfaces ..................18-4 18-4. Active (TFT) Interface ..................18-5 18-5. The MPC823e LCD System ................18-6 18-6. LCD Controller Block Diagram ............... 18-7 18-7. LCD Functional Module ................. 18-8 18-8. Grayscale Generation .................. 18-11 18-9.
Page 43 21-2. TAP Controller State Machine ................21-3 21-3. Output Pin Cell (O.Pin) ...................21-4 21-4. Observe-Only Input Pin Cell (I.Obs) ...............21-5 21-5. Output Control Cell (IO.CTL) ................21-5 21-6. General Arrangement of Bidirectional Pin Cells ..........21-6 21-7. Bypass Register ...................21-20 MOTOROLA MPC823e REFERENCE MANUAL...
Page 44: List Of Tables
External Signals 2-1. Signal Descriptions ..................2-2 2-2. Pin Breakout ....................2-13 Section 3 Memory Map 3-1. MPC823e Internal Memory Map ..............3-1 Section 4 Reset 4-1. Possible Reset Results ..................4-1 Section 5 Clocks and Power Control 5-1. Power-On Reset Clock Configuration ............5-13 5-2.
Page 45 13-3. Data Bus Contents for Write Cycles .............13-27 13-4. BURST/TSIZE Encoding ................13-33 13-5. Address Space Definitions ................13-34 13-6. Termination Signal Protocol .................13-46 Section 14 Endian Modes 14-1. Little-Endian Effective Address Modification For Individual Aligned Scalar ......................14-1 MOTOROLA MPC823e REFERENCE MANUAL xliv...
Page 46 16-11. FIR5 Parameter Packet ................16-53 16-12. FIR6 Parameter Packet ................16-57 16-13. IIR Parameter Packet ................... 16-59 16-14. MOD Parameter Packet ................16-62 16-15. DEMOD Parameter Packet ................16-64 16-16. LMS1 Parameter Packet ................16-67 MPC823e REFERENCE MANUAL MOTOROLA...
Page 47 16-45. Prioritization of CPM Interrupt Sources ............16-507 16-46. Encoding the Interrupt Vector ..............16-510 Section 17 PCMCIA Interface 17-1. Card Enable as Driven by the MPC823e ............17-3 17-2. Host Programming for Memory Cards ............17-7 17-3. Host Programming For I/O Cards ..............17-7 Section 18LCD Controller 18-1.
Page 48 20-12. Development Support Register Protection ........... 20-41 Section 21 IEEE 1149.1 Test Access Port 21-1. Boundary Scan Bit Definition ................. 21-7 21-2. Instruction Decoding ..................21-19 Appendix A Serial Communication Performance A-1. MPC823e Performance Table .................A-3 xlvii MPC823e REFERENCE MANUAL MOTOROLA...
Page 49: Features
SECTION 1 INTRODUCTION The MPC823e microprocessor is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of portable electronic products. It is a version of the low-cost MPC823 with larger instruction and data caches, which will provide for greater PowerPC core performance.
Page 50 DSP Functions are Supported by ROM or Download Microcode and the Communication Processor Module DSP Capabilities, Include but are No Limited to JPEG Compression/Decompression • Four Independent Baud Rate Generators and Two Input Clock Pins for Supplying Clocks to the SCC and SMC Serial Channels MPC823e REFERENCE MANUAL MOTOROLA...
Page 51 • Four Independent 16-Bit Timers That can be Configured as Two 32-Bit Timers. • Interrupts Seven External Interrupt Request (IRQ) Lines One Nonmaskable Interrupt Twelve Port Pins with Interrupt Capability Ten Internal Interrupt Sources Programmable Highest Priority Request MOTOROLA MPC823e REFERENCE MANUAL...
Page 52 — Supports Interlace/Noninterlace Scanning Methods — Programmable Display Active Area — Programmable Background Color for Inactive Area — Glueless Interface for Most Digital Video Encoders — Uses Burst Read DMA Cycles for Maximum Bus Performance — End-of-Frame Interrupt Generation MPC823e REFERENCE MANUAL MOTOROLA...
Page 53 Power-Down—All Units are Disabled Including PLL, but not the Real-Time Clock and Periodic Interrupt Timer, Timebase, and Decrementer. Saves More Power than Other Modes. The State of Certain Registers may be Preserved. Can be Dynamically Shifted Between High and Low Frequency Operation MOTOROLA MPC823e REFERENCE MANUAL...
Page 54: Architecture
I/O support needed for high-speed digital communications. The MPC823e is comprised of four main modules that interface with the 32-bit internal bus: • The embedded PowerPC core •...
Page 55 Introduction Figure 1-1. MPC823e Block Diagram MOTOROLA MPC823e REFERENCE MANUAL...
Page 56: The Embedded Powerpc Core
32K and 256M. The memory controller has 0 to 20 wait states for each bank of memory and can use address type matching to qualify each memory bank access. It provides four byte-enable signals for varying width devices, one output-enable signal, and one boot chip-select that is available at reset. MPC823e REFERENCE MANUAL MOTOROLA...
Page 57: The Communication Processor Module
The DRAM controller supports page mode access for successive transfers within bursts. Although the MPC823e supports a glueless interface to DRAM, the capacitance of the system bus may require that there be external buffers. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking for a maximum of seven refresh cycles.
Page 58: The Video/Lcd Controller
Introduction 1.2.4 The Video/LCD Controller The MPC823e has a dual-purpose video/LCD controller that shares common dual-port memory. You can only run one of the controllers at a time. 1.2.4.1 THE VIDEO CONTROLLER. The video controller can be used to drive a digital NTSC/PAL encoder or a wide variety of digital LCD panels.
Page 59: Power Management
The MPC823e microprocessor can compare using the =, ≠, <, and > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events.
Page 60: Differences Between Mpc823 (Rev B) And Mpc823E
• A time-division multiplex channel (TDMB) was added to the serial interface 1.8 MPC823e GLUELESS SYSTEM DESIGN The MPC823e was primarily designed to make it easy for you to interface a microprocessor with other system components. Figure 1-2 illustrates a system configuration that contains one flash EPROM and yet supports DRAM SIMM and one SRAM.
Page 61 Introduction 8-BIT BOOT EPROM/FLASH ADDRESS ADDRESS GPL1/ 0:3] DATA DATA DRAM MPC823e ADDRESS [0:3] DATA PARITY[0:3] PARITY[0:3] SRAM ADDRESS DATA Figure 1-2. MPC823e System Configuration MOTOROLA MPC823e REFERENCE MANUAL 1-13...
Page 62: External Signals
SECTION 2 EXTERNAL SIGNALS This section briefly describes each of the MPC823e input and output signals. VDDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS/KAPWR A[6:31] USBRXD/PA[15] TSIZ0/REG USBOE/PA[14] TSIZ1 RXD2/PA[13] RD/WR TXD2/PA[12] BURST SMRXD2/L1TXDA/PA[9] BDIP/GPL_B5 SMTXD2/L1RXDA/PA[8] TIN1/L1RCLKA/BRGO1/CLK1/PA[7] TIN3/L1RCLKB/TOUT1/CLK2/PA[6] TIN2/L1TCLKA/BRGO2/CLK3/PA[5] TIN4/L1TCLKB/TOUT2/CLK4/PA[4] IRQ2/RSV LCD_A/SPISEL/PB[31] IRQ4/KR/RETRY/SPKROUT SPICLK/TXD3/PB[30] SPIMOSI/RXD3/PB[29] D[0:31] BRGO3/SPIMISO/PB[28]...
Page 63: The System Bus Signals
This signal is driven by the MPC823e when it is the owner of the bus. It is input when an external master initiates a transaction on the bus and it is sampled internally to allow the memory controller/PCMCIA interface to control the accessed slave device.
Page 64 Transfer Error Acknowledge —This open-drain signal indicates that a bus error occurred in the current transaction. It is driven asserted by the MPC823e when the bus monitor does not detect a bus cycle termination within a reasonable amount of time.
Page 65 D[16:23] by transferring to a slave device initiated by IRQ5 the MPC823e. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus.
Page 66 PCMCIA Slot B are handled by the PCMCIA interface. Write Enable 0 —This output signal is asserted when a write access to an external slave controlled by the GPCM in the memory controller is initiated by the MPC823e. BS_AB0...
Page 67 Address Strobe —This input pin is driven by an external asynchronous master to indicate a valid address on the A[6:31] lines. The memory controller in the MPC823e will synchronize this signal and control the memory device addressed if it is recognized to be under its control.
Page 68 IP_B0 Input Port B 0 —This input signal is sensed by the MPC823e and its value and changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Page 69 PIN NUMBER DESCRIPTION IP_B6 Input Port B 6—This input signal is sensed by the MPC823e and its value and changes are reported in the PIPR and PSCR registers of the PCMCIA interface. DSDI Development Serial Data Input—This input signal is the data in for the debug port interface.
Page 70 CTS3—The Clear to Send Modem line for serial communication controller 3. SDACK1 SDACK1—The SDMA acknowledge 1 output pin that is used as a peripheral L1RSYNCB interface signal for IDMA emulation. L1RSYNCB—The transmit sync input for the serial interface time-division multiplex port B. MOTOROLA MPC823e REFERENCE MANUAL...
Page 71 CTS2—The Clear to Send Modem line for serial communication controller 2. PC[8] General-Purpose I/O Port C Bit 8—Bit 8 of the general-purpose I/O port C. CD2—The Carrier Detect Modem line for serial communication controller 2. TGATE1 TGATE1—The timer1/timer2 gate signal. 2-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 72 General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose I/O port D. LD0—One of the 12 data bus bits used to drive the LCD panel. FIELD FIELD—The line the video controller uses to signal which of the two fields is the current one. MOTOROLA MPC823e REFERENCE MANUAL 2-11...
Page 73 Development Serial Data Output—This output signal is the data out of the debug port interface. TRST Test Reset—This input signal is the asynchronous reset of the TAP machine on the JTAG interface. See Table 2-2 No Connect—These pins are not connected. for pin breakout. 2-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 74 External Signals Table 2-2. Pin Breakout SIGNAL PIN NUMBER ADDRESS BUS PINS MOTOROLA MPC823e REFERENCE MANUAL 2-13...
Page 75 External Signals Table 2-2. Pin Breakout (Continued) SIGNAL PIN NUMBER DATA BUS PINS 2-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 76 G5, G12, H5, H12, J5, J12, K5, K12, L5, L12, M5–M12 VDDL A7, G1, J16, T7 VDDSYN KAPWR VSSSYN VSSSYN1 F6–F11, G6–G11, H6–H11, J6–J11, K6–K11, L6–L11 NO CONNECT PINS A16, C1, C6, E14, J13, N9, N13, P1, P10 MOTOROLA MPC823e REFERENCE MANUAL 2-15...
Page 77: Memory Map
SECTION 3 MEMORY MAP This section discusses the internal memory map (including key registers) of the MPC823e. Each memory resource is mapped within a contiguous block of 16K storage. The location of this block within the global 4G real storage space can be mapped on 64K resolution through an implementation specific special register called the internal memory map register (IMMR).
Page 78 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION POR3—PCMCIA Interface Option Register 3 17-17 PBR4—PCMCIA Interface Base Register 4 17-16 POR4—PCMCIA Interface Option Register 4 17-17 PBR5—PCMCIA Interface Base Register 5 17-16 POR5—PCMCIA Interface Option Register 5...
Page 79 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION BR7—Base Register Bank 7 15-9 OR7—Option Register Bank 7 15-11 140 to 163 RES—Reserved — — MAR—Memory Address Register 15-26 MCR—Memory Command Register...
Page 80 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SYSTEM INTEGRATION TIMERS KEYS TBSCRK—Timebase Status and Control Register Key 5-27 TBREFFUK—Timebase Reference Register Upper Key 5-27 TBREFFLK—Timebase Reference Register Lower Key 5-27 TBK—Timebase and Decrementer Register Key...
Page 81 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION VFCR1—Video Frame Configuration Register (Set 1) 19-13 VFAA1—Video Frame Buffer A Start Address Register (Set 1) 19-14 VFBA1—Video Frame Buffer B Start Address Register (Set 1)
Page 82 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION IDMR1—IDMA1 Mask Register 16-95 915 to 917 RES—Reserved — — IDSR2—IDMA2 Status Register 16-94 919 to 91B RES—Reserved — — IDMR2—IDMA2 Mask Register...
Page 83 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION CPM TIMERS TGCR—Timer Global Configuration Register 16-77 982 to 98F RES—Reserved — — TMR1—Timer1 Mode Register 16-78 TMR2—Timer2 Mode Register 16-78 TRR1—Timer1 Reference Register 16-79 TRR2—Timer2 Reference Register...
Page 84 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION RCTR3—RISC Controller Trap Register 3 — RCTR4—RISC Controller Trap Register 4 — 9D4 to 9D5 RES—Reserved — — RTER—RISC Timer Event Register...
Page 85 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL COMMUNICATION CONTROLLER 2 GSMR_L—SCC2 General Mode Low Register 16-166 GSMR_H—SCC2 General Mode High Register 16-166 PSMR—SCC2 Protocol-Specific Mode Register 16-176 16-217 (UART)
Page 86 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SCCE—SCC3 Event Register 16-187 16-227 (UART) 16-250 (HDLC) 16-284 (AHDLC) 16-314 (Trans) A52-A53 Reserved — SCCM—SCC3 Mask Register 16-187 16-229 (UART) 16-253 (HDLC)
Page 87 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL PERIPHERAL INTERFACE SPMODE—SPI Mode Register 16-443 RES—Reserved — SPIE—SPI Event Register 16-452 AA7 to AA9 RES—Reserved — — SPIM—SPI Mask Register 16-453 RES—Reserved...
Page 88 Memory Map Table 3-1. MPC823e Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION DUAL-PORT RAM 2000 to 2FFF DPRAM—Dual-Port RAM 4,096 bytes — 3000 to 3BFF DPRAM—Dual-Port RAM Expansion — — 3C00 to 3FFF PRAM—Parameter RAM 1,024 bytes —...
Page 89: Reset
SECTION 4 RESET The reset block of the MPC823e has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
Page 90: Types Of Reset
When PORESET is asserted, the MPC823e enters the power-on reset (POR) state in which SRESET and HRESET are asserted by the core. When the MPC823e remains in POR, the extension counter of 512 is reset, and the MODCK pins are sampled when POR pin is negated.
Page 91: External Hard Reset
Reset 4.1.2 External Hard Reset HRESET (hard reset) is a bidirectional, active low I/O pin. The MPC823e can only detect an external assertion of HRESET if it occurs while the MPC823e is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft reset) is a bidirectional, active low I/O pin.
Page 92: External Soft Reset
Trace Window End Address for more information. If the DSCK pin is asserted during SRESET negation, the processor will take a breakpoint exception and go directly to debug mode, instead of fetching the reset vector. MPC823e REFERENCE MANUAL MOTOROLA...
Page 93: Reset Status Register
The 32-bit reset status register (RSR) is powered by the keep-alive power supply. As shown in Section 3 Memory Map , it is memory-mapped into the MPC823e system interface unit register map and receives its default reset values at power-on reset.
Page 94 1, but a write of zero has no effect on it. 0 = No JTAG reset event occurred. 1 = A JTAG reset event occurred. Bits 8–31—Reserved These bits are reserved and must be set to 0. MPC823e REFERENCE MANUAL MOTOROLA...
Page 95: How To Configure Reset
4.3.1 Hard Reset When a hard reset event occurs, the MPC823e reconfigures its hardware system as well as the development port configuration. The logical value of the bits that determine its initial mode of operation are sampled either from the data bus or from an internal default constant (D[0:31]=x’00000000).
Page 96 RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-2. Reset Configuration Sampling Scheme For Short PORESET Assertion CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-3. Reset Configuration Sampling Scheme For Long PORESET Assertion MPC823e REFERENCE MANUAL MOTOROLA...
Page 97 Reset MOTOROLA MPC823e REFERENCE MANUAL...
Page 98: Hard Reset Configuration Word
1 = The memory controller is not activated after reset, but it is cleared. BPS—Boot Port Size This field defines the port size of the boot device. 00 = 32-bit port size. 01 = 8-bit port size. 10 = 16-bit port size. 11 = Reserved. 4-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 99 IP_B3/IWP2/VF2 functions as VF2. IP_B4/LWP0/VF0 functions as VF0. IP_B5/LWP1/VF1 functions as VF1. OP2/MODCK1/STS functions as STS. ALE_B/DSCK/AT1 functions as AT1. IP_B2/AT2 functions as AT2. IP_B6/DSDI/AT0 functions as AT0. IP_B7/PTR/AT3 functions as AT3. OP3/MODCK2/DSDO functions as OP3. MOTOROLA MPC823e REFERENCE MANUAL 4-11...
Page 100: Soft Reset
The EBDF bits (described in Section 5.2.1 System Clock and Reset Control Register ) are initialized during HRESET using the hard reset configuration mechanism. 4.3.2 Soft Reset When a soft reset event occurs, the MPC823e reconfigures the development port. 4-12 MPC823e REFERENCE MANUAL...
Page 101: Clocks And Power Control
MPC823e clock module. For additional timer information, refer to Section 12 System Interface Unit . The MPC823e has a variety of programmable modes that allow your system to operate at its highest level, and yet it still gives you the option of operating in a power-saving mode.
Page 102 (÷4 OR ÷16 ) DIVIDERS CLOCK BRGCLK DRIVERS LCDCLK SYNCCLK CLKOUT CLKOUT DRIVER TBCLK TMBCLK TMBCLK DRIVER RTDIV RTSEL ÷4 RTC /PIT CLOCK PITRTCLK AND DRIVER XTAL MAIN CLOCK EXTAL ÷512 OSCILLATOR (OSCM) Figure 5-1. Clock Source and Distribution MPC823e REFERENCE MANUAL MOTOROLA...
Page 103: Register Model
5.2 REGISTER MODEL 5.2.1 System Clock and Reset Control Register The SPLL has a 32-bit control register that is powered by keep-alive power. The system clock and reset control register (SCCR) is memory-mapped into the MPC823e system interface unit’s register map. SCCR...
Page 104 1 = The system switches to high frequency when there is a pending interrupt from the interrupt controller or POW bit in the machine state register is cleared. Bits 11–12 and 15–16—Reserved These bits are reserved and must be set to 0. MPC823e REFERENCE MANUAL MOTOROLA...
Page 105 This field sets the VCOOUT frequency division factor for general system clocks to be used in low-power mode. In low-power mode, the MPC823e automatically switches to the DFNL frequency. To select the DFNL frequency, load this field with the divide value and set the CSRC bit.
Page 106 This field sets the VCOOUT frequency division factor for general system clocks to be used in normal mode. In normal mode, the MPC823e automatically switches to the DFNH frequency. To select the DFNH frequency, load this field with the divide value and clear the CSRC bit.
Page 107: Pll, Low-Power, And Reset Control Register
DFNH bits is 0x0 (divide-by-one). When the SPLL is operating in one-to-one mode, the MF field is set to 0. See Table 5-2 for details. Bits 12–15—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL...
Page 108 This bit specifies whether the DFNH or DFNL field generates the general system clock. This bit is cleared by a hard reset. 0 = The general system clock is generated by the DFNH field. 1 = The general system clock is generated by the DFNL field. MPC823e REFERENCE MANUAL MOTOROLA...
Page 109 This bit indicates when the address and data external pins are driven by an internal pull-down device in sleep and deep-sleep mode. 0 = No pull-down on the address and data bus. 1 = Address and data bus is driven low in sleep and deep-sleep mode. MOTOROLA MPC823e REFERENCE MANUAL...
Page 110: The Clock Module
The MPC823e clock module consists of the main crystal oscillator, the SPLL, the low-power divider, the clock generator/driver blocks, and the clock module/system low-power control block.
Page 111 DFNH GCLK1 GCLK2 UPM, PCMCIA, DFNL EXTERNAL GCLK1_50 EBDF INTERFACE PHASE GCLK2_50 LOW-POWER MODE CLKOUT COM[0:1] LCDCLK LCD/VIDEO CONTROLLER LCDCLK50 DFLCD DFALCD LCD PANEL DIVISION FACTOR TOTAL LESS THAN 64 Figure 5-3. Clock Module Diagram MOTOROLA MPC823e REFERENCE MANUAL 5-11...
Page 112: On-Chip Oscillators And External Clock Input
Lower frequency clock input reduces the overall electromagnetic interference generated by the system. Also, oscillating at different frequencies reduces the cost because you will not have to add more oscillators to your system. The MPC823e SPLL block diagram is illustrated in Figure 5-4.
Page 113: Spll Stability
For input frequencies greater than 15MHz and MF ≤ 2, this skew is between -0.9ns and +0.9ns. Otherwise, this skew is not guaranteed. However, for MF<10 and input frequencies greater than 10MHz, the skew is between -2.3ns and +2.3ns. MOTOROLA MPC823e REFERENCE MANUAL 5-13...
Page 114: The Low-Power Clock Divider
SYNCCLK, LCDCLK, LCDCLK50, BRGCLK, and GCLKx (which is sent to the rest of the MPC823e). GCLKxC is the system timing reference for the core, instruction and data caches, and memory management unit. GCLKx is the system timing reference for the other modules.
Page 115 The low-power dividers allow you to reduce and restore the operating frequencies of different sections of the MPC823e without losing the SPLL lock. Using the low-power dividers, you can still obtain full chip operation, but at a lower frequency. This is called normal low mode.
Page 116: Internal Clock Signals
GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50—are the basic clocks supplied to all modules of the MPC823e. GCLKxC is supplied to the core, data and instruction caches, and memory management unit. It is not active when the core is in sleep or power-down mode.
Page 117 EBDF bit in the SCCR. GCLK2_50 always rises simultaneously with GCLK2. GCLK1_50 rises simultaneously with GCLK1, but when the MPC823e is not in normal low mode, the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50 and EBDF determines the division factor between GCLKx and GCLKx_50.
Page 118 GCLK1 DIVIDED BY 4 GCLK2 DIVIDED BY 4 Figure 5-8. Divided System Clocks Timing Diagram GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 5-9. MPC823e Clocks For Division Factor 2 5-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 119 MPC823e is operating at a reduced frequency. Refer to Section 16.8 The Baud Rate Generators for more information about using the baud rate generator clock to save power.
Page 120: The Baud Rate Generator Clock
MPC823e is operating at a reduced frequency. This allows you to maintain the serial synchronization circuitry at the preferred rate, while lowering the general system clock to the lowest possible rate.
Page 121: The Lcd Clocks
LCDCLK DIVIDE BY 1 LCDCLK50 DIVIDE BY 1 GCLK2 DIVIDE BY 2 LCDCLK DIVIDE BY 2 LCDCLK50 DIVIDE BY 2 GCLK2 DIVIDE BY 4 LCDCLK DIVIDE BY 4 LCDCLK50 DIVIDE BY 4 Figure 5-14. LCD Clock Timing Diagram MOTOROLA MPC823e REFERENCE MANUAL 5-21...
Page 122: Clock Configuration
Clocks and Power Control 5.3.5 Clock Configuration You can configure the clock of the MPC823e using the MODCK1 and MODCK2 pins. The SPLL has several power and ground pins (VDDSYN, VSSSYN, VSSSYN1, and XFC) that must be properly terminated for stability and CLKOUT integrity.
Page 123: The System Phase-Locked Loop Pins
5.3.5.2 THE SYSTEM PHASE-LOCKED LOOP PINS. The internal frequency of the MPC823e and the output of the CLKOUT pin depends on the quality of the crystal circuit and the MF bit in the PLPRCR. The SPLL contains the following dedicated pins that are isolated from common power and ground.
Page 124: Power Control
Clocks and Power Control 5.4 POWER CONTROL To preserve the life of your battery, the MPC823e provides low-power modes that limit the operation to essential modules. In addition to normal high mode, the MPC823e supports normal low, doze high, doze low, sleep, deep-sleep, and power-down modes. When the communication processor module is idle, it uses its own power-saving mechanism to shut down automatically.
Page 125: Keep-Alive Power
5% in power-down mode 5.4.2 Keep-Alive Power When the MPC823e is in normal operation mode, the keep-alive power supply (KAPWR) is powered to the same voltage value as that of the I/O buffers and logic. Therefore, if the VDDL and VDDH is 3.3V, then the KAPWR is 2.9V to 3.3V.
Page 126: Power Switching Example
If VDDL is fed with 3.3V, SW2 and SW3 can be combined into one switch. The TEXP pin, if enabled, is asserted by the MPC823e when the real-time clock or timebase time value matches the value programmed in its associated alarm register or when the periodic interrupt timer or decrementer decrements their value to zero.
Page 127 Clocks and Power Control 5.4.2.2 REGISTER LOCK. The MPC823e registers that are powered by KAPWR can be write-protected using the associated key register shown in Table 5-6. When the MPC823e disconnects from the main power supply after it enters power-down mode, the value of these registers is automatically preserved.
Page 128: Low-Power Operation
The PLPRCR is described in Section 5.2.2 PLL, Low-Power, and Reset Control Register . The MPC823e uses an interrupt to exit from any of these lower power modes. An enabled interrupt clears the LPM field, but does not change the CSRC bit. An interrupt switches automatically to normal high mode from normal low, doze high, doze low, sleep, or deep-sleep mode.
Page 129 ** TEXPS RECEIVES THE ZERO VALUE BY WRITING A ONE TO IT. WRITING A ZERO HAS NO EFFECT ON TEXPS. *** YOU CAN SWITCH FROM NORMAL HIGH TO NORMAL LOW ONLY IF THE CONDITIONS TO AN INTERRUPT ARE CLEARED. Figure 5-18. MPC823e Low-Power Mode Flowchart MOTOROLA...
Page 130 GCLK1 clocks. Once the interrupt is recognized, it takes between two and four GCLK1 clocks for the MPC823e to reach normal high mode. For example, it could take between 10.24µs and 20.48µs to wake up in a 75MHz system where DFNL = 111 (divided by 256).
Page 131 In normal and doze modes, the system can be in the high mode defined by the DFNH field or in the low mode defined by the DFNL field. The MPC823e is in normal high mode after reset and this also the default state when the condition to exit low-power mode occurs.
Page 132: The Powerpc Core
In addition, it contains part of the development support features of the MPC823e, including breakpoint and watchpoint support, program flow tracking data generation, and debug mode operation in which the core is controlled by the development support system through the debug port module.
Page 133: Basic Structure Of The Core
The instruction queue is always flushed when the history buffer is recovered. An instruction retires from the machine after it finishes executing without exception and all preceding instructions are retired from the machine. Figure 6-1 illustrates the core’s microarchitecture. MPC823e REFERENCE MANUAL MOTOROLA...
Page 134 (32 X 32) HISTORY IDIV ADDR DATA SOURCE BUSES (4 SLOTS / CLOCK) Figure 6-1. Block Diagram of the Core RETIRE EXECUTION UNITS WRITEBACK HISTORY BUFFER ISSUE BRANCH INSTRUCTION QUEUE UNIT FETCH Figure 6-2. Instruction Flow Conceptual Diagram MOTOROLA MPC823e REFERENCE MANUAL...
Page 135: Basic Instruction Pipeline
The sequencer data path is illustrated in Figure 6-4. In addition, the sequencer implements all branch processor instructions, including flow control and condition register instructions. MPC823e REFERENCE MANUAL MOTOROLA...
Page 136: Flow Control
Branches enter the queue to mark watchpoints. See Section 20 Development Capabilities and Interface for details. Since branches do not prevent the issue of sequential instructions unless they come in pairs, the performance impact of entering branches in the instruction prefetch queue is negligible. MOTOROLA MPC823e REFERENCE MANUAL...
Page 137: Issuing Instructions
The execution units then decode the instruction, interrogate the register unit (if the operands and targets are free), and inform the sequencer that it accepts the instruction for execution. MPC823e REFERENCE MANUAL MOTOROLA...
Page 138: Interrupts
The core interrupts can be generated when an exception occurs. An exception results when certain instructions are executed or an asynchronous external event occurs. There are five exception sources in the MPC823e: • External interrupt request • Certain memory access conditions (protection faults and bus error) •...
Page 139: Implementing The Precise Exception Model
Instructions remain in the queue until they complete execution and all preceding instructions have been completed to a point where no exception can be generated (in the core, such a condition is fulfilled by waiting for full completion). MPC823e REFERENCE MANUAL MOTOROLA...
Page 140 If so, instruction issue waits until the long latency operation finishes. The following types of instructions can potentially cause the history buffer to fill: • Floating-point arithmetic instructions • Integer divide instructions • Instructions that affect or use resources external to the core (load/store instructions) MOTOROLA MPC823e REFERENCE MANUAL...
Page 141: Restartability After An Interrupt
A write of any data to these locations performs the operation specified in the following table. Any read from these locations is treated like any other unimplemented instruction and, therefore, results in an implementation-dependent software emulation interrupt. 6-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 142: Processing An Interrupt
At time point E the machine state register and instruction pointer of the executing process have been saved and control has been transferred to the interrupt handler routine. MOTOROLA MPC823e REFERENCE MANUAL 6-11...
Page 143: Serialization
This can be either divide, load, or store a multiple, string, or pair of simple load/store instructions. 6-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 144: The External Interrupt
6.3.7 The External Interrupt The core provides one external interrupt line: the architectural maskable external interrupt. In the MPC823e, this interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by the MSR bit, which is automatically cleared by the hardware to disable external interrupts when any interrupt is taken.
Page 145: Interrupt Ordering
NOTES: The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second instruction. This, of course, refers to this second instruction. Exclusive for any one instruction. 6-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 146: The Register Unit
• Decodes the operand fields of all sequential instructions • Drives the operand buses, as requested by the execution unit • Performs scoreboard checking and signing • Samples the resulting data from the writeback bus MOTOROLA MPC823e REFERENCE MANUAL 6-15...
Page 147: Control Registers
The PowerPC Core 6.4.1 Control Registers The following tables describe the core control registers, also known as special-purpose registers, implemented within the MPC823e. Table 6-7. Standard Special-Purpose Registers REGISTER PRIVILEGED SERIALIZE ACCESS NAME DECIMAL 00000 00001 Write: Full Sync Read:...
Page 148 Synch Relative to Load/Store Operations 00100 11110 ICTRL Debug Fetch Sync on Write 00100 11111 Debug Write: Fetch Sync Read: Synch Relative to Load/Store Operations 10011 10110 DPDR Debug Read and Write 10011 10111 Fetch DPIR MOTOROLA MPC823e REFERENCE MANUAL 6-17...
Page 149 Refer to Section 20.6.2 Development Port Registers. Protection of registers with “debug” privileges is described in Section 20.6.1 Protecting the Development Port Registers. This register is a fetch-only register. Using mtspr is ignored and using mfspr gives an undeﬁned value. 6-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 150: Physical Location Of Special Registers
For these registers, a bus cycle is performed on the internal bus with the following address. 0:17 18:22 23:27 28:31 0000 If any address error occurs on this cycle, an implementation-dependent software emulation interrupt is taken. MOTOROLA MPC823e REFERENCE MANUAL 6-19...
Page 151: Powerpc Standard Control Register Bit Assignment
EE—External Interrupt Enable This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed. 6-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 152 1 = The interrupt prefix is 0xFFFn_nnnn. IR—Instruction Relocate This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed. MOTOROLA MPC823e REFERENCE MANUAL 6-21...
Page 153: The Condition Register
• Bit 0—Negative (LT). The result is negative. • Bit 1—Positive (GT). The result is positive. • Bit 2—Zero (EQ). The result is zero. • Bit 3—Summary Overflow (SO). The values of this bit is copied from XER 6-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 154: Fixed-Point Exception Cause Register
Otherwise, it is cleared. Bits 3–24—Reserved These bits are reserved and must be set to 0. BCNT—Byte Count for Load/Store String Operations This field specifies the number of bytes to be transferred by a lswx or stswx instruction. MOTOROLA MPC823e REFERENCE MANUAL 6-23...
Page 155: Initializing The Control Registers
The divide instructions have a relatively long latency, but those instructions can update the OV bit in the XER after one cycle. Therefore, data dependency on the XER is limited to one cycle, although the divide instruction latency can be a maximum of 11 clocks. 6-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 156: The Load/Store Unit
2-entry, 32-bit wide queue that holds fixed-point data. The load/store unit has a dedicated writeback bus so that loaded data received from the internal bus is written directly back to the fixed- or floating-point register files. MOTOROLA MPC823e REFERENCE MANUAL 6-25...
Page 157: Issuing Load/Store Instructions
Then, using a dedicated interface, the load/store unit notifies the integer unit of the need to calculate the effective address. All load/store instructions are executed and terminated in order. 6-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 158: Serializing Load/Store Instructions
When executing speculative load cycles to the nonspeculative external memory region, no external cycles are generated until the load instruction becomes nonspeculative. MOTOROLA MPC823e REFERENCE MANUAL 6-27...
Page 159: Executing Unaligned Instructions
04’h 00’h 2 BUS CYCLES 04’h 00’h 2 BUS CYCLES 04’h 00’h 3 BUS CYCLES 04’h 00’h 3 BUS CYCLES 04’h Figure 6-7. Number of Bus Cycles Needed For Unaligned, Single Register Fixed-Point Load/Store Instructions 6-28 MPC823e REFERENCE MANUAL MOTOROLA...
Page 160: Little-Endian Mode Support
The MPC823e storage reservation supplies hooks for the support of storage reservation implementation in a hierarchical bus structure. For a full description of the storage reservation mechanism, refer to Section 7 PowerPC Architecture Compliance.
Page 161: Instruction Timing
Location of Special Registers for detailed information. If the access terminates in a bus error, then an implementation-dependent software emulation interrupt is taken. All write operations to off-core special registers (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. 6-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 162: Storage Control Instructions
Instruction Information Undefined Implementation Dependent Software Emulation Does Not Change Does Not Change Undefined Interrupt Floating-Point Unavailable Interrupt Does Not Change Does Not Change Undefined Program Interrupt Does Not Change Does Not Change Does Not Change MOTOROLA MPC823e REFERENCE MANUAL 6-31...
Page 163: Powerpc Architecture Compliance
Illegal and reserved instruction class instructions are supported by implementation-dependent code and, thus the core hardware generates the implementation-dependent software emulation interrupt. How the core treats invalid and preferred instruction forms is described in the specific processor compliance sections. MOTOROLA MPC823e REFERENCE MANUAL...
Page 164: Exceptions
• Move to/from system register instructions All hardware instructions are defined for the fixed-point processor in the PowerPC User Instruction Set Architecture (Book I) . For details about the performance of the various instructions, see Table 8-1 of this manual. MPC823e REFERENCE MANUAL MOTOROLA...
Page 165: Fixed-Point Arithmetic Instructions
In the cmpi , cmp , cmpli , and cmpl instructions, the L bit is applicable for 64-bit implementations. For the MPC823e, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0.
Page 166: Storage Synchronization Instructions
The MPC823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx instructions is in the writethrough required mode.
Page 167: The Effect Of Operand Placement On Performance
7.2.3 The Storage Control Instructions The MPC823e interprets the cache control instructions ( icbi , isync , dcbt , dcbi , dcbf , dcbz , dcbst , eieio , and dcbtst ) as if they pertain only to the MPC823e cache. These instructions do not broadcast.
Page 168: Timebase
7.3.1 The Branch Processor 7.3.1.1 MACHINE STATE REGISTER. The floating-point exception mode is ignored by the MPC823e. The IP bit initial state after reset is set as programmed by the reset configuration specified in Section 12 System Interface Unit. 7.3.1.2 PROCESSOR VERSION REGISTER. The value of the PVR register’s version field is x’0050’.
Page 169: Reference And Change Bits
• Supports fast software tablewalk mechanism 7.3.4 Reference and Change Bits No reference bit is supported by the MPC823e. However, the change bit is supported by using the data TLB error interrupt mechanism when writing to an unmodified page. 7.3.5 Storage Protection Two main protection modes are supported by the MPC823e: •...
Page 170: Processing
01200 Implementation-Dependent Data TLB Miss 01300 Implementation-Dependent Instruction TLB Error 01400 Implementation-Dependent Data TLB Error 01500 - 01BFF Reserved 01C00 Implementation-Dependent Data Breakpoint 01D00 Implementation-Dependent Instruction Breakpoint 01E00 Implementation-Dependent Peripheral Breakpoint 01F00 Implementation-Dependent Nonmaskable Development Port MPC823e REFERENCE MANUAL MOTOROLA...
Page 171: System Reset Interrupt
(MSR =1) it is taken. If SRR1 Bit 30 =1, the interrupt is recoverable and the following registers are set. SRR0—Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. MOTOROLA MPC823e REFERENCE MANUAL...
Page 172: Data Storage Interrupt
• The operand of a lwarx or stwcx is not word aligned. • The operand of a load/store individual scalar instruction is not naturally aligned when MSR = 1. • An attempt to execute a multiple/string instruction is made when MSR = 1. 7-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 173: Program Interrupt
PowerPC Architecture Compliance 7.3.7.3.6 Program Interrupt. The MPC823e cannot generate a floating-point exception type interrupt. Likewise, an illegal instruction type program interrupt is not generated by the core, but an implementation-dependent software emulation interrupt is generated instead. A privileged instruction program interrupt is generated for an on-core valid special-purpose...
Page 174: Implementation-Dependent Software Emulation Interrupt
=1 and you try to fetch an instruction from a page whose effective page number cannot be translated by TLB. The following registers are set: SRR0–Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. 7-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 175: Implementation-Specific Instruction Tlb Error Interrupt
Set to 1 when Bit 4 is set. Otherwise, set to 0. 11–15 Set to 0. Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR MOTOROLA MPC823e REFERENCE MANUAL 7-13...
Page 176: Implementation-Specific Data Tlb Miss Interrupt
• An attempt was made to write to a page with a negated change bit. The following registers are set: SRR0—Save/Restore Register 0 Set to the effective address of the instruction that caused the interrupt. 7-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 177: Implementation-Specific Debug Register
• When a peripheral breakpoint request is presented to the interrupt mechanism. • When the development port request is presented to the interrupt mechanism. Refer to Section 20 Development Capabilities and Interface for details on how to generate the development port request. MOTOROLA MPC823e REFERENCE MANUAL 7-15...
Page 178 The execution resumes from an address equal to the base indicated by the MSR and the following offset. • x’01D00’–For an instruction breakpoint match • x’01C00’–For a data breakpoint match • x’01E00’–For a development port maskable request or a peripheral breakpoint • x’01F00’–For a development port nonmaskable request 7-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 179: Partially Executed Instructions
In the MPC823e, the instruction can be partially executed only in the case of load/store instructions that cause multiple access to the memory subsystem—multiple/string and unaligned load/store instructions.
Page 180: Instruction Execution Timing
LDST Serialize + 1 Special Registers: mtspr, mttb, mttbu Move from External to the Core Load Latency LDST Special Registers: mfspr, mftb, mftbu Move from Special Registers — See List Located Internal to the Core: mfspr MOTOROLA MPC823e REFERENCE MANUAL...
Page 181 Serialize + 1 Serialize + 1 LDST Yes (Before) Register (Debug, DAR, DSISR): mtspr, mfspr String Instructions: Serialize + 1 Serialize + 1 LDST lswi, lswx, stswi, stswx + Number + Number of Words of Words Accessed Accessed MPC823e REFERENCE MANUAL MOTOROLA...
Page 182 Although a store (as well as mtspr for special registers external to the core) issued to the load/store unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until the bus is free. MOTOROLA MPC823e REFERENCE MANUAL...
Page 183: Instruction Execution Timing Examples
This causes a bubble to occur in the instruction stream as shown in the execute line. Refer to Section 8.2.2.2 Private Writeback Bus Load for instances in which no such dependency exists. MPC823e REFERENCE MANUAL MOTOROLA...
Page 184: Writeback
GCLK1 MULLI ADDIC FETCH MULLI ADDIC DECODE MULLI SUB, MULLI ADDIC READ + EXECUTE MULLI WRITEBACK Figure 8-3. Another Example of a Writeback Arbitration MOTOROLA MPC823e REFERENCE MANUAL...
Page 185: Private Writeback Bus Load
CACHE ADDRESS LOAD WRITEBACK E ADDRESS E DATA Figure 8-4. Example of a Private Writeback Bus Load The load and the xor writeback in the same clock since they use the writeback bus in two different ticks. MPC823e REFERENCE MANUAL MOTOROLA...
Page 186: Fastest External Load (Data Cache Miss)
Figure 8-5. Example of an External Load The sub instruction is dependent on the value read by the load. It causes three bubbles in the instruction execution stream. The external clock is shifted 90 ° relative to the internal clock. MOTOROLA MPC823e REFERENCE MANUAL...
Page 187: A Full History Buffer
It takes one more bubble from the load writeback to allow further issue. This is the time for the history buffer to retire sub, add, and and. MPC823e REFERENCE MANUAL MOTOROLA...
Page 188: Branch Folding
The issue of the branch itself is referred to as a bubble since no actual work is done by a branch. MOTOROLA MPC823e REFERENCE MANUAL...
Page 189: Branch Prediction
The fetched instructions on the predicted path are not allowed to execute before the condition is finally resolved. Instead, they are stacked in the instruction prefetch queue. 8-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 190: Instruction Cache
SECTION 9 INSTRUCTION CACHE The MPC823e instruction cache is a 16K four-way, set associative storage area. It is organized into 256 sets, four lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical code segments that need fast and deterministic execution time.
Page 191 • Tags and Data Arrays can be Accessed by the Core for Debugging and Testing Purposes • Special Support is Available when the MPC823e Processor is in Debug Mode. Refer to Section 9.9 Debug Support for More Information. MPC823e REFERENCE MANUAL...
Page 192 TAG254 W0 W1 W2 W3 SET255 TAG255 W0 W1 W2 W3 COMP COMP COMP COMP HIT1 HIT2 HIT3 HIT0 BIDIRECTIONAL MUX 4-> 1 TO LINE BUFFER/ FROM BURST BUFFER Figure 9-1. Instruction Cache Organization Block Diagram MOTOROLA MPC823e REFERENCE MANUAL...
Page 193: Programming The Instruction Cache
• Instruction cache address register (IC_ADR) • Instruction cache data port register (read-only) (IC_DAT) These registers are privileged and any attempt to access them while the core is in the problem state (MSR =1) results in a program interrupt. MPC823e REFERENCE MANUAL MOTOROLA...
Page 194: Instruction Cache Control And Status Register
011 = LOAD & LOCK . 100 = UNLOCK LINE . 101 = UNLOCK ALL . 110 = INVALIDATE ALL . 111 = Reserved. Bits 7–9—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL...
Page 195: Instruction Cache Address Register
RESET — NOTE: — = Undefined. ADR—Address This field represents the address to be used in the command programmed in the CMD field of the IC_CST. The format may vary depending on the selected cache operation. MPC823e REFERENCE MANUAL MOTOROLA...
Page 196: Instruction Cache Data Port Register
When a cache hit occurs, bits 28-29 of the instruction address are used to select one word from the cache line whose tag matches the instruction pointer. The instruction is then immediately transferred to the instruction unit of the core. MOTOROLA MPC823e REFERENCE MANUAL...
Page 197: Instruction Cache Miss
To minimize power consumption, the MPC823e instruction cache does not initiate a miss sequence in most cases when the instruction is inside a predicted path. The MPC823e instruction cache evaluates fetch requests to see if they are inside a predicted path and if a hit is detected, the requested data is delivered to the core.
Page 198: Invalidating The Instruction Cache
MPC823e instruction cache. This instruction does not broadcast on the external bus and the MPC823e does not snoop this instruction if it is broadcasted by other masters. This command is not privileged and has no associated error cases. The instruction cache performs this instruction in one clock cycle.
Page 199: Loading And Locking The Instruction Cache
This command has no error cases that you need to check. The instruction cache performs this instruction in one clock cycle. To accurately calculate the latency of this instruction, bus latency must be taken into consideration. 9-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 200: Unlocking The Entire Instruction Cache
Instructions that originate in a cache-inhibited region and are stored in the burst buffer can be sent to the MPC823e core no more than once before being refetched. In the memory management unit, a memory region can be programmed as cache-inhibited. When...
Page 201: Instruction Cache Read
Instruction Cache 9.4.6 Instruction Cache Read The MPC823e allows you to read all data stored in the instruction cache, including the content of the tags array. However, this operation is privileged and any attempt to perform it when the core is in the problem state (MSR =1) results in a program interrupt.
Page 202 These bits are reserved and must be set to 0. V—Valid Entry 0 = Entry is not valid. 1 = Entry is valid. L—Lock Entry 0 = Entry is unlocked. 1 = Entry is locked. MOTOROLA MPC823e REFERENCE MANUAL 9-13...
Page 203: Instruction Cache Write
Bit 29—When set, way 1 is more recently used than way 0. 9.4.7 Instruction Cache Write Instruction cache write is only enabled when the MPC823e is in test mode. 9.5 RESTRICTIONS Zero wait state devices that are placed on the internal bus are considered to be in the cache-inhibited memory region and the hardware correct operation trusts the software to follow the exact steps mentioned in Section 9.7 Updating Code And Memory Region...
Page 204: Debug Support
The MPC823e can be debugged either in debug mode or by a software monitor debugger. In both cases, the core of the MPC823e CPU asserts the internal freeze (FRZ) signal. When FRZ is asserted the instruction cache treats all misses as if they were from cache-inhibited regions and, assuming the debug routine is not in the instruction cache, the cache state remains exactly the same.
Page 205: Data Cache
SECTION 10 DATA CACHE The MPC823e data cache is a 8K two-way, set-associative cache. It is organized into 256 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical data segments that need a fast and deterministic execution time.
Page 206: Organization Of The Data Cache
TAG254 W0 W1 W2 W3 SET255 TAG255 W0 W1 W2 W3 TAG255 W0 W1 W2 W3 COMP COMP HIT1 HIT0 BIDIRECTIONAL MUX 2 -> 1 TO/FROM LINE BUFFER/ BURST BUFFER Figure 10-1. Data Cache Organization 10-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 207: Programming The Data Cache
The following PowerPC instructions are supported by the data cache. 10.3.1.1 P PC USER INSTRUCTION SET ARCHITECTURE (BOOK I) OWER The data cache supports the sync instruction through a cache pipe clean indication to the core. MOTOROLA MPC823e REFERENCE MANUAL 10-3...
Page 208: Powerpc Virtual Environment Architecture (Book Ii)
OWER data cache supports the dcbi (data cache block invalidate) instruction. 10.3.2 Implementation-Specific Operations The MPC823e data cache includes some extended features in addition to those of the PowerPC architecture. The following are implementation-specific operations supported by the MPC823e: • Block lock •...
Page 209 1 = Address munging performed by the core is reversed before accessing the data cache, the instruction cache and storage. Byte swap is performed for the instruction and data caches’ external accesses. This bit is a read-only bit and any attempt to write to it is ignored. MOTOROLA MPC823e REFERENCE MANUAL 10-5...
Page 210 This field is sticky and set by the hardware. It is read-only and cleared when read. 0 = No Error. 1 = Error. Bits 13–31—Reserved These bits are reserved and must be set to 0. 10-6 MPC823e REFERENCE MANUAL MOTOROLA...
Page 211: Reading The Cache Structures
10.3.3.3 READING THE CACHE STRUCTURES. To read the data stored in the data cache tags or registers, follow these steps: 1. Write to the DC_ADR. This register can also be read for debugging purposes. 2. Read the DC_DAT register. MOTOROLA MPC823e REFERENCE MANUAL 10-7...
Page 212 • 0 × 04—Copyback address register When reading from the DC_DAT register, the 20 bits of the tag (and related information) that is selected by the DC_ADR are placed in the targeted general-purpose register. The 10-8 MPC823e REFERENCE MANUAL MOTOROLA...
Page 213 1 = This entry is aged or least-recently used. D—Dirty or Clean Cache Line 0 = This entry has not been modified since it was read from memory. 1 = This entry has been modified since it was read from memory. MOTOROLA MPC823e REFERENCE MANUAL 10-9...
Page 214: Operating The Data Cache
The cache operates in either writethrough or copyback mode, depending on how the memory management unit is programmed. If two logical blocks map to the same physical block, it is considered a programming error for them to specify different cache write policies. 10-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 215: Copyback Mode
(the dirty line ﬂush error is an imprecise interrupt). For more information about reading the address and data of a line, see Section 10.3.1.2 PowerPC Virtual Environment Architecture (Book II). MOTOROLA MPC823e REFERENCE MANUAL 10-11...
Page 216: Writethrough Mode
10.4.4 Data Cache Freeze The MPC823e can be debugged either in debug mode or by a software monitor debugger. In both cases, the MPC823e core asserts the internal FRZ signal. For a detailed description of MPC823e debug support, refer to Section 20 Development Capabilities and Interface.
Page 217: Data Cache Coherency
10.5 DATA CACHE COMMANDS 10.5.1 Flushing and Invalidating the Cache The MPC823e allows the data cache to be flushed and invalidated when it is being controlled by the software. The data cache can be invalidated by writing the UNLOCK ALL and INVALIDATE ALL commands to the DC_CST.
Page 218: Data Cache Instructions
The MPC823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx. instructions is in the Write Through Required mode.
Page 219: Memory Management Unit
SECTION 11 MEMORY MANAGEMENT UNIT The MPC823e implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. This implementation includes separate instruction and data memory management units. The MPC823e memory management unit is compliant with the PowerPC Microprocessor...
Page 220: Address Translation
In the MPC823e, the table lookup and TLB reload are performed by a software routine with little hardware assistance. This partition simplifies the hardware and gives the system the opportunity to choose the translation table structure.
Page 221: Protection
IMPLEMENTATION REAL PAGE NUMBER BYTE SPECIFIC NO ACCESS ERROR INTERRUPTS TO CORE PROTECTION TRANSLATION TRANSLATION LOOKUP ENABLED ENABLED TABLE EXCEPTION LOGIC 32-BIT REAL ADDRESS Figure 11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages MOTOROLA MPC823e REFERENCE MANUAL 11-3...
Page 222: Storage Control
Control Register and Section 11.6.1.2 MMU Data Control Register for details. The MPC823e does not generate an exception for a reference bit update because there is no entry for a reference bit in the translation lookaside buffer. The change bit updates are implemented by the software, but the hardware treats the change bit as a write-protect attribute.
Page 223: Translation Table Structure
Memory Management Unit 11.5 TRANSLATION TABLE STRUCTURE The MPC823e memory management unit includes special hardware to assist in a two-level software tablewalk. Other table structures are not precluded. Figure 11-2 and Figure 11-3 illustrate the two levels of translation table structures supported by MPC823e special hardware.
Page 224 20 - FOR 4K LEVEL TWO DESCRIPTOR 1023 18 - FOR 16K 13 - FOR 512K 9 - FOR 8M REAL PAGE ADDRESS PAGE OFFSET REAL ADDRESS Figure 11-2. Two Level Translation Table When MD_CTR(TWAM) = 1 11-6 MPC823e REFERENCE MANUAL MOTOROLA...
Page 225 LEVEL TWO DESCRIPTOR 1023 20 - FOR 4K 18 - FOR 16K 13 - FOR 512K 9 - FOR 8M REAL PAGE ADDRESS PAGE OFFSET REAL ADDRESS Figure 11-3. Two Level Translation Table When MD_CTR(TWAM) = 0 MOTOROLA MPC823e REFERENCE MANUAL 11-7...
Page 226 Table 11-2. Number of Identical Entries Required in the Level One Table PAGE SIZE MD_CTR MD_CTR TWAM TWAM — 512K Table 11-3. Number of Identical Entries Required in the Level Two Table PAGE SIZE MD_CTR MD_CTR TWAM TWAM — 512K 1,024 1,024 11-8 MPC823e REFERENCE MANUAL MOTOROLA...
Page 227: Level One Descriptor
PS—Page Size Level One 00 = Small (4K or 16K). 01 = 512K. 11 = 8M. 10 = Reserved. WT—Writethrough Attribute for Entry 0 = Copyback cache policy region (default). 1 = Writethrough cache policy region. MOTOROLA MPC823e REFERENCE MANUAL 11-9...
Page 228: Level Two Descriptor
INSTRUCTION PAGES DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE PRIVILEGED MODE PROBLEM MODE No access No access No access No access Executable No access Read/Write No access Executable Executable Read/Write Read-only Executable Executable Read/Write Read/Write 11-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 229 INSTRUCTION PAGES DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE PRIVILEGED MODE PROBLEM MODE No access No access No access No access Executable No access Read/Write No access Executable Executable Read/Write Read-only Executable Executable Read/Write Read/Write MOTOROLA MPC823e REFERENCE MANUAL 11-11...
Page 230 Executable Read/Write Read-only Executable Executable Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: Mx_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid 11-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 231 Executable Read/Write Read-only Executable Executable Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: Mx_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-13...
Page 232 This bit is the cache-inhibit attribute for the entry. Setting this bit will inhibit cache fill for accesses to this page. V—Valid This is the page valid bit. Setting this bit indicates the page is valid or resident in the memory (for demand page memory management). 11-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 233: Programming The Memory Management Unit
Instruction MMU Debug CAM MD_DCAM Data MMU Debug CAM MI_DRAM0 Instruction MMU Debug RAM0 MD_DRAM0 Data MMU Debug RAM0 Instruction MMU Debug RAM1 Data MMU Debug RAM1 MI_DRAM1 MD_DRAM1 Figure 11-4. Organization of the Memory Management Unit Registers MOTOROLA MPC823e REFERENCE MANUAL 11-15...
Page 234: Control Registers
0 = Ignore problem/privilege state during address compare. 1 = Consider problem/privilege state according to MI_RPN[24:27]. Bits 7–18—Reserved These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read. 11-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 235: Mmu Data Control Register
This bit is the data cache attributes default value when the data MMU is disabled (MSR = 0). RSV4D—Reserve Four Data TLB Entries 0 = DTLB_INDX decremented modulo 32. 1 = DTLB_INDX decremented modulo 28. MOTOROLA MPC823e REFERENCE MANUAL 11-17...
Page 236: Mmu Current Address Space Id Register
Bits 0–27—Reserved These bits are reserved and must be set to 0. Ignored on a write. CASID—Current Address Space ID This field is compared to the ASID field of a TLB entry to qualify a match. 11-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 237: Mmu Instruction Effective Page Number Register
0 = The TLB entry is invalid. 1 = The TLB entry is valid. ASID—Address Space ID This field represent the address space ID of the instruction TLB entry to be compared with the CASID field of the M_CASID register. MOTOROLA MPC823e REFERENCE MANUAL 11-19...
Page 238: Mmu Data Effective Page Number Register
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read. ASID—Address Space ID This field is the address space IDs of the TLB entry to be compared with the CASID field of the M_CASID register. 11-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 239: Mmu Instruction Real Page Number Register
PP2 field, the same protection code has different protection schemes. 4K PAGES WITH 1K RESOLUTION PROTECTION INSTRUCTION PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Executable No access Executable Executable Executable Executable MOTOROLA MPC823e REFERENCE MANUAL 11-21...
Page 240 This field contains a protection code for the second subpage in a 4K page. Depending on the encoding mode, this field has different meanings. 4K PAGES WITH 1K RESOLUTION PROTECTION INSTRUCTION PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Executable No access Executable Executable Executable Executable 11-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 241 Executable No access Executable Executable Executable Executable PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MI_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-23...
Page 242 Executable No access Executable Executable Executable Executable PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MI_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid 11-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 243 0 = This entry matches only if the ASID filed in the TLB entry matches the value of the M_CASID register. 1 = ASID comparison is disabled for the entry. CI—Cache Inhibit This bit is the cache-inhibit attribute for the TLB entry. V—Valid This bit indicates that a TLB entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-25...
Page 244: Mmu Data Real Page Number Register
PP2 field, the same protection code has different protection schemes. 4K PAGES WITH 1K RESOLUTION PROTECTION DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Read/Write No access Read/Write Read-only Read/Write Read/Write 11-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 245 This field contains a protection code for the second subpage in a 4K page. Depending on the encoding mode, this field has different meanings. 4K PAGES WITH 1K RESOLUTION PROTECTION DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Read/Write No access Read/Write Read-only Read/Write Read/Write MOTOROLA MPC823e REFERENCE MANUAL 11-27...
Page 246 Read/Write No access Read/Write Read-only Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MD_CTR (PPCS) = 0 First subpage not valid First subpage valid Second subpage not valid Second subpage valid 11-28 MPC823e REFERENCE MANUAL MOTOROLA...
Page 247 Read/Write No access Read/Write Read-only Read/Write Read/Write PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MD_CTR (PPCS) = 0 Third subpage not valid Third subpage valid Fourth subpage not valid Fourth subpage valid MOTOROLA MPC823e REFERENCE MANUAL 11-29...
Page 248 0 = This entry matches only if the ASID filed in the TLB entry matches the value of the M_CASID register. 1 = ASID comparison is disabled for a TLB entry. CI—Cache Inhibit This bit is the cache-inhibit attribute for a TLB entry. V—Valid This bit indicates that a TLB entry is valid. 11-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 249: Mmu Instruction Access Protection Register
(Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for 32-Bit Microprocessors manual: 00 = All accesses are considered privileged. 01 = Access permission defined by page protection bits. 10 = Problem and privileged interpretation is swapped. 11 = All accesses are considered problem. MOTOROLA MPC823e REFERENCE MANUAL 11-31...
Page 250: Mmu Data Access Protection Register
(Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for 32-Bit Microprocessors manual: 00 = All accesses are considered privileged. 01 = Access permission defined by page protection bits. 10 = Problem and privileged interpretation is swapped. 11 = All accesses are considered problem. 11-32 MPC823e REFERENCE MANUAL MOTOROLA...
Page 251: Mmu Instruction Tablewalk Control Register
0 = Unguarded storage. 1 = Guarded storage. PS—Page Size Level One Default value on instruction TLB miss is 00. 00 = Small (4K or 16K). 01 = 512K. 11 = 8M. 10 = Reserved. MOTOROLA MPC823e REFERENCE MANUAL 11-33...
Page 252: Mmu Data Tablewalk Control Register
MD_EPN[12:21] when MD_CTR = 0. TWAM G—Guarded When written, this bit of the entry has the following settings and is set to 0 on a data TLB miss: 0 = Unguarded storage. 1 = Guarded storage. 11-34 MPC823e REFERENCE MANUAL MOTOROLA...
Page 253 When written, this bit has the following settings and is set to 1 on a data TLB miss. When this bit is read, it returns a zero. 0 = Entry is invalid. 1 = Entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-35...
Page 254: Mmu Tablewalk Base Register
This field is ignored on write. It returns MD_EPN[0:9] on read when MD_CTR = 1 and TWAM MD_EPN[2:11] when MD_CTR = 0. TWAM Bits 30–31—Reserved These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read. 11-36 MPC823e REFERENCE MANUAL MOTOROLA...
Page 255: Mmu Tablewalk Special Register
The values of the MD_CAM, MD_RAM0, and MD_RAM1 registers can be read using the mfspr instruction. If you try to write to the MD_RAM0 and MD_RAM1 registers using the mtspr instruction, it will be considered a NOP (no operation) instruction. MOTOROLA MPC823e REFERENCE MANUAL 11-37...
Page 256: Mmu Data Cam Entry Read Register
0 = Subpage 2 (address[20:21] = 10) is not valid. 1 = Subpage 2 (address[20:21] = 10) is valid. For Bit 23: 0 = Subpage 3 (address[20:21] = 11) is not valid. 1 = Subpage 3 (address[20:21] = 11) is valid. 11-38 MPC823e REFERENCE MANUAL MOTOROLA...
Page 257: Mmu Data Ram Entry Read Register 0
— ADDR SPR 825 FIELD APGI RESERVED RESET — — — — — — ADDR SPR 825 NOTE: — = Undefined. RPN—Real Page Number These bits are the most-significant bits of the page’s physical address. MOTOROLA MPC823e REFERENCE MANUAL 11-39...
Page 258 0 = Copyback data cache policy page entry. 1 = Writethrough data cache policy page entry. CI—Cache-Inhibit When this bit is 0, it is not cache-inhibited. Bits 30–31—Reserved These bits are reserved and must be set to 0. 11-40 MPC823e REFERENCE MANUAL MOTOROLA...
Page 259: Mmu Data Ram Entry Read Register 1
MMU interrupt invocation. Software must take an appropriate action before setting this bit to 1. 1 = Changed region. Write access is allowed to this page. EVF—Entry Valid Flag 0 = Entry is invalid. 1 = Entry is valid. MOTOROLA MPC823e REFERENCE MANUAL 11-41...
Page 260 1 = Subpage 2 (address[20:21]=10) problem write access is permitted. URP3—Problem (User) Read Permission Page Three 0 = Subpage 3 (address[20:21]=11) problem read access is not permitted. 1 = Subpage 3 (address[20:21]=11) problem read access is permitted. 11-42 MPC823e REFERENCE MANUAL MOTOROLA...
Page 261: Mmu Instruction Content-Addressable Registers
FIELD RESET — ADDR SPR 816 FIELD ASID RESET — — — — — ADDR SPR 816 NOTE: — = Undefined. EPN—Effective Page Number These bits are the most-significant bits of the page’s effective address. MOTOROLA MPC823e REFERENCE MANUAL 11-43...
Page 262 1 = Subpage 1 (address[20:21]=01) is valid. Bit 30: 0 = Subpage 2 (address[20:21]=10) is not valid. 1 = Subpage 2 (address[20:21]=10) is valid. Bit 31: 0 = Subpage 3 (address[20:21]=11) is not valid. 1 = Subpage 3 (address[20:21]=11) is valid. 11-44 MPC823e REFERENCE MANUAL MOTOROLA...
Page 263: Mmu Instruction Ram Entry Read Register 0
100 = Reserved. 101 = Reserved. 110 = Reserved. CI—Cache-Inhibit When this bit is 0, it is not cache-inhibited. APG—Access Protection Group A maximum of 16 protection groups are supported and represented in one’s compliment format. MOTOROLA MPC823e REFERENCE MANUAL 11-45...
Page 264: Mmu Instruction Ram Entry Read Register 1
MI_CAM register. MI_RAM1 FIELD RESERVED RESET ADDR SPR 818 FIELD RESERVED RESET — — — ADDR SPR 818 NOTE: — = Undefined. Bits 0–25—Reserved These bits are reserved and must be set to zero. 11-46 MPC823e REFERENCE MANUAL MOTOROLA...
Page 265: Interrupts
The software tablewalk code is responsible for loading the translation information of the missed page from the translation table that resides in the memory. Refer to Section 11.8.1.1 Translation Reload Examples for more information. MOTOROLA MPC823e REFERENCE MANUAL 11-47...
Page 266: Implementation-Specific Instruction Tlb Error
The data storage interrupt status register indicates the cause of the data TLB error interrupt. For bit assignments refer to Section 7.3.7.3.14 Implementation-Specific Data TLB Error Interrupt. It is the software’s responsibility to invoke the data storage interrupt handler. 11-48 MPC823e REFERENCE MANUAL MOTOROLA...
Page 267: Manipulating The Translation Lookaside Buffer
• Performs a write to the TLB entry by loading the tablewalk level two entry value to the MI_RPN or MD_RPN register. • A special register (M_TW) is available for the software tablewalk routine, in addition to the PowerPC architecture’s special registers (SPRG0–SPRG3). Using this register allows for more efficient interrupt handling. MOTOROLA MPC823e REFERENCE MANUAL 11-49...
Page 268: Translation Reload Examples
# load R1 with level two pointer # while taking into account the # page size R1, (R1) # Load level two page entry mtspr MI_RPN, R1 # Write TLB entry mfspr R1, M_TW # restore R1 11-50 MPC823e REFERENCE MANUAL MOTOROLA...
Page 269: Controlling The Tlb Replacement Counter
TLB reload. 11.8.3 Invalidating the Translation Lookaside Buffer The MPC823e implements the tlbie instruction to invalidate the TLB entries. This instruction invalidates TLB entries in the translation lookaside buffer that hits, including the reserved entries. Notice that with 4K page size, the 22 most-significant bits of the effective address are used in the comparison because no segment registers are implemented.
Page 270: Requirements For Accessing The Memory Management Unit Control Registers
All instruction and data memory management unit control registers must be accessed when instruction and data address translation is turned off. Prior to an mtspr MD_DBCAM receive instruction, an eieio instruction must be placed and executed before you write to the Mx_CAM register. 11-52 MPC823e REFERENCE MANUAL MOTOROLA...
Page 271: System Interface Unit
The external bus interface handles the transfer of information between internal buses and the memory or peripherals in the external address space. The MPC823e is designed to allow external bus masters to request and obtain mastership of the system bus. For additional information on bus operation, see Section 13 External Bus Interface .
Page 272: Features
PCMCIA socket with a maximum of eight memory or I/O windows. Note: Both the MPC823e and MPC821 have the same PCMCIA module except that the MPC823e has only one valid slot (Slot B). Programming a window to be assigned to Slot A may cause an erroneous operation.
Page 273 (RTCAL) register. The real-time clock is clocked by the PITRTCLK clock. • Freeze Support —The system interface unit determines whether the software watchdog timer, periodic interrupt timer, timebase, decrementer, and real-time clock will continue to run in freeze mode. MOTOROLA MPC823e REFERENCE MANUAL 12-3...
Page 274 Figure 12-1 illustrates a block diagram of the system configuration and protection logic. MODULE CONFIGURATION MONITOR PERIODIC INTERRUPT INTERRUPT TIMER SOFTWARE INTERRUPT OR WATCHDOG TIMER SYSTEM RESET POWERPC CLOCK INTERRUPT DECREMENTER POWERPC INTERRUPT TIMEBASE COUNTER REAL-TIME INTERRUPT CLOCK Figure 12-1. System Configuration and Protection Logic 12-4 MPC823e REFERENCE MANUAL MOTOROLA...
Page 275: Interrupt Configuration
System Interface Unit 12.3 INTERRUPT CONFIGURATION Many aspects of MPC823e system configuration are controlled by the SIU module configuration register (SIUMCR). The SIUMCR primarily controls the external bus arbitration logic, external master support, and pin multiplexing. See Section 12.12.1.1 SIU Module Configuration Register for more information.
Page 276: Priority Of The Interrupt Sources
00001100 IRQ2 00010000 Level 2 00010100 IRQ3 00011000 Level 3 00011100 IRQ4 00100000 Level 4 00100100 IRQ5 00101000 Level 5 00101100 IRQ6 00110000 Level 6 00110100 IRQ7 00111000 Lowest Level 7 00111100 16-31 Reserved — 12-6 MPC823e REFERENCE MANUAL MOTOROLA...
Page 277: Programming The Interrupt Controller
When set, this field indicates a pending internal level interrupt of a corresponding value. See Figure 12-2 for more information. 0 = The appropriate interrupt is not pending. 1 = The appropriate interrupt is pending. MOTOROLA MPC823e REFERENCE MANUAL 12-7...
Page 278: Siu Interrupt Mask Register
IRQx interrupt is falling edge-triggered or low logical level triggered. The WMx field in the SIEL register determines if the corresponding IRQx interrupt will cause the MPC823e to exit low-power mode. Note: IRQ0 will generate a non-maskable interrupt even if its corresponding IRM0 bit is not set.
Page 279: Siu Interrupt Edge/Level Register
When the EDx bit is 0, a low logical level in the IRQx signal is an interrupt request. The WMx bit, if set, indicates that a low level detection in the corresponding interrupt request line causes the MPC823e to exit low-power mode. SIEL...
Page 280: Siu Interrupt Vector Register
INTC—Interrupt Code This field indicates the highest priority pending interrupt. Bits 8–31—Reserved These bits are reserved and must be set to 0. The value equals the interrupt number multiplied by four. See Table 12-1 for details. 12-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 281: The Bus Monitor
The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The MPC823e system interface unit provides a bus monitor option that monitors internally generated external bus accesses on the external bus. At the start of the transfer start (TS) signal, the monitor begins counting and stops when the transfer acknowledge (TA) or transfer error (TEA) signal is asserted.
Page 282: The Powerpc Decrementer
This binary counter is clocked by the same frequency as the timebase. In the MPC823e, the decrementer is clocked by the TMBCLK clock, so you must enable the TBE bit in the TBSCR for the decrementer to start.
Page 283: Decrementer Register
FIELD RESET — NOTE: — = Undefined. DEC—Decrementer This field is used by a down counter to cause decrementer interrupts. A read of this register always returns the current count value from the down counter. MOTOROLA MPC823e REFERENCE MANUAL 12-13...
Page 284: The Powerpc Timebase
There is no interrupt or other indication generated when the count rolls over. The period of the timebase depends on the driving frequency. For the MPC823e, the timebase is clocked by the TMBCLK clock and the period for the timebase is:...
Page 285: Timebase Reference Registers
(IMMR & 0xFFFF0000) + 0x204 FIELD TBREFU RESET — ADDR (IMMR & 0xFFFF0000) + 0x206 NOTE: — = Undefined. TBREFU—Timebase Reference Upper These bits represent the 32-bit reference value for the upper part of the timebase. MOTOROLA MPC823e REFERENCE MANUAL 12-15...
Page 286: Timebase Status And Control Register
If set, these bits indicate that a match has been detected between the corresponding reference register (TBREFU for REFA and TBREFL for REFB) and the timebase low register. Each bit must be cleared by writing a 1. 12-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 287: The Real-Time Clock
RTCK register. Refer to Section 5.4.2 Keep-Alive Power for more information. RTSEC INTERRUPT CLOCK DIVIDE PITRTCLK 32-BIT COUNTER DISABLE BY 8,192 CLOCK ALARM DIVIDE BY 9,600 INTERRUPT 32-BIT REGISTER Figure 12-4. Real-Time Clock Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 12-17...
Page 288: Real-Time Clock Status And Control Register
1 = Assumes that it is driven by a 38.4kHz crystal. SIE—Seconds Interrupt Enable This bit allows the real-time clock to generate an interrupt when the SEC bit is set. 0 = Disables seconds interrupt. 1 = The real-time clock generates an interrupt. 12-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 289: Real-Time Clock Register
RESET — ADDR (IMMR & 0xFFFF0000) + 0x224 FIELD RESET — ADDR (IMMR & 0xFFFF0000) + 0x226 NOTE: — = Undefined. RTC—Real-Time Clock This field represents time measured in seconds. Each unit represents one second. MOTOROLA MPC823e REFERENCE MANUAL 12-19...
Page 290: Real-Time Clock Alarm Seconds Register
RTCSC is set to zero. PITRTCLK is assumed to be 8192Hz (4.192MHz/512 or 32.768KHz/4). 9600 = the 38K field of the RTCSC is set to one. PITRTCLK is assumed to be 9,600Hz (38.4KHz/4). Bits 14–31—Reserved These bits are reserved and must be set to 0. 12-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 291: Real-Time Clock Alarm Register
This field indicates that an alarm interrupt will be generated as soon as there is a match between this field and the corresponding bits in the RTC register. The alarm has a 1 second resolution. MOTOROLA MPC823e REFERENCE MANUAL 12-21...
Page 292: The Periodic Interrupt Timer
Solving this equation using a 32.768kHz external clock gives: PITC 1 PITperiod ------------------------ - 8192 This gives a range from 122 microseconds with a PITC of 0x0000 to a maximum of 8 seconds with a PITC of 0xFFFF. 12-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 293: Periodic Interrupt Status And Control Register
0 = The periodic interrupt timer is unaffected by the FRZ signal. 1 = The FRZ signal stops the periodic interrupt timer. PTE—Periodic Timer Enable 0 = The periodic interrupt timer is disabled. 1 = The periodic interrupt timer is enabled. MOTOROLA MPC823e REFERENCE MANUAL 12-23...
Page 294: Periodic Interrupt Timer Count Register
This field contains the count for the periodic timer. If this field is loaded with the value 0xFFFF, the maximum count period will be selected. Bits 16–31—Reserved These bits are reserved and must be set to 0. 12-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 295: Periodic Interrupt Timer Register
NOTE: — = Undefined. PIT—Periodic Interrupt Timing Count This field contains the current count remaining for the periodic timer. Writes have no effect on this field. Bits 16–31—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 12-25...
Page 296: The Software Watchdog Timer
Figure 12-7 also shows the range that the value in the SWTC field determines. This value is then loaded into a 16-bit decrementer clocked by the system clock. When necessary, an additional divide by 2,048 prescaler is used. 12-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 297: Software Service Register
0xAA39 must be written to this register. The SWSR can be written at any time, but returns all zeros when read. SWSR FIELD RESET ADDR (IMMR & 0xFFFF0000) + 0x00E SEQ—Sequence This field is the pattern that is used to control the state of the software watchdog timer. MOTOROLA MPC823e REFERENCE MANUAL 12-27...
Page 298: Freeze Operation
The periodic interrupt timer, decrementer, and timebase are not influenced by these low-power modes and they continue to run at their respective frequencies. These timers can generate an interrupt to bring the MPC823e out of the low-power modes.
Page 299: Multiplexing The System Interface Unit Pins
System Interface Unit 12.11 MULTIPLEXING THE SYSTEM INTERFACE UNIT PINS Due to the limited number of pins available in the MPC823e package, some of the functionalities share pins. The actual MPC823e pinout is illustrated in Section 2 External Signals. The following table shows how the functionality is controlled on each pin.
Page 300: Programming The System Interface Unit
ICTRL register. Refer to Section 20.6.2 Development Port Registers for more information. This bit is locked by the DLK bit. 0 = Disable show cycles for all internal data cycles. 1 = Show address and data of all internal data cycles. 12-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 301 Section 4.3.1.1 Hard Reset Configuration Word. 00 = ALE_B/DSCK/AT1 functions as defined by DBGC. IP_B6/DSDI/AT0 functions as defined by DBGC. OP3/MODCK2/DSDO functions as defined by DBGC. IP_B7/PTR/AT3 functions as defined by DBGC. TCK/DSCK functions as DSCK. MOTOROLA MPC823e REFERENCE MANUAL 12-31...
Page 302 OPAR = 0. PNCS—Parity Enable For Nonmemory Controller Regions This bit enables parity generation/checking for memory regions not controlled by the MPC823e memory controller. DPC—Data Parity Pins Configuration This bit configures the functionality of the DP[0:3]/IRQ[3:6] pins. 0 = DP[0:3]/IRQ[3:6] functions as IRQ[3:6].
Page 303 If it is reset, the memory controller ignores the value of the TS pin when it does not own the external bus. When the MPC823e owns the bus, the memory interprets the assertion of the TS pin as an internal request.
Page 304: Internal Memory Map Register
However, it would not change if the part is revised to fix a bug in an existing module. The MPC823e has a part number of 0x24. The other byte of information reflects the revision number. Refer to our website for the corresponding revision number for your particular version of the silicon.
Page 305: System Protection Control Register
BMT—Bus Monitor Timing This field defines the timeout period, in 8 system clock resolution, for the bus monitor. The maximum timeout is 2,040 clocks. Bits 25–27—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 12-35...
Page 306: Transfer Error Status Register
RESERVED IEXT ITMT IPB0 IPB1 IPB2 IPB3 RESERVED DEXT DTMT DPB0 DPB1 DPB2 DPB3 RESET ADDR (IMMR & 0xFFFF0000) + 0x022 Bits 0–17 and 24–25—Reserved These bits are reserved and must be set to 0. 12-36 MPC823e REFERENCE MANUAL MOTOROLA...
Page 307 Parity check for a memory region that is not controlled by the memory controller is enabled by the PNCS bit in the SIUMCR, as shown in Section 12.12.1.1 SIU Module Configuration Register. MOTOROLA MPC823e REFERENCE MANUAL 12-37...
Page 308: External Bus Interface
The MPC823e bus is synchronous, but the bus and control input signals must be timed to setup and hold times relative to the rising edge of the clock. In this situation, bus cycles can be completed in two clock cycles.
Page 309 External Bus Interface Furthermore, for all inputs, the MPC823e latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in Figure 13-1, where tsu and tho are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, the input must be stable during the sample window.
Page 310: Control Signals
External Bus Interface 13.2.1 Control Signals The MPC823e initiates a bus cycle by driving the address, size, address type, cycle type, and read/write outputs. At the beginning of a bus cycle, the TSIZ0 and TSIZ1 signals are driven with the AT signals. TSIZx indicates the number of bytes to be transferred during an operand cycle that consists of one or more bus cycles.
Page 311: Bus Signal Descriptions
DESCRIPTION ADDRESS AND TRANSFER ATTRIBUTES A[6:31] High Address Bus —Driven by the MPC823e when it owns the external bus. It specifies the physical address of the bus transaction. These signals can change during a transaction when controlled by the memory controller.
Page 312 D[8:15] D[16:23] D[24:31] Driven by the MPC823e when it owns the external bus and has initiated a write transaction to a slave device. For single beat transactions, if external A[6:31] and TSIZ[0:1] do not select the byte lanes for transfer, they will not supply valid data.
Page 313 D[8:15] D[16:23] D[24:31] Driven by the MPC823e when it owns the external bus and has initiated a write transaction to a slave device. Each parity signal has the parity value (even or odd) of the corresponding data bus byte. For single beat...
Page 314: Bus Interface Operation
CLKOUT output signal. All signals for the MPC823e bus interface are specified with respect to the rising-edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge.
Page 315: Basic Transfers
13.4.1 Basic Transfers The basic transfer protocol defines the sequence of actions that must occur on the MPC823e bus to perform a complete bus transaction. The chronological sequence or phase of a typical bus transfer is as follows: 1. Arbitration 2.
Page 316: Single Beat Read Flow
ASSERTS BUS BUSY (BB) IF NO OTHER MASTER IS DRIVING ASSERT TRANSFER START (TS) DRIVES ADDRESS AND ATTRIBUTES RECEIVES ADDRESS RETURNS DATA ASSERTS TRANSFER ACKNOWLEDGE (TA) RECEIVES DATA Figure 13-3. Basic Flow Diagram of a Single Beat Read Cycle MOTOROLA MPC823e REFERENCE MANUAL 13-9...
Page 317 External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA DATA IS VALID Figure 13-4. Single Beat Read Cycle–Basic Timing–Zero Wait States 13-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 318 External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA WAIT STATE DATA IS VALID Figure 13-5. Single Beat Read Cycle–Basic Timing–One Wait State MOTOROLA MPC823e REFERENCE MANUAL 13-11...
Page 319: Single Beat Write Flow
ASSERTS BUS BUSY (BB) IF NO OTHER MASTER IS DRIVING ASSERT TRANSFER START (TS) DRIVES ADDRESS AND ATTRIBUTES RECEIVES ADDRESS DRIVES DATA RECEIVES DATA ASSERTS TRANSFER ACKNOWLEDGE (TA) STOPS DRIVING DATA Figure 13-6. Basic Flow Diagram of a Single Beat Write Cycle 13-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 320 External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA DATA IS SAMPLED Figure 13-7. Single Beat Write Cycle–Basic Timing–Zero Wait States MOTOROLA MPC823e REFERENCE MANUAL 13-13...
Page 321 CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA WAIT STATE DATA IS SAMPLED Figure 13-8. Single Beat Write Cycle of One Wait State 13-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 322 A typical single beat transfer assumes that the external memory has a 32-bit port size. The MPC823e provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size memories, thus allowing transfers to these devices when they are controlled by the internal memory controller.
Page 323: Burst Transfers
For this type of bus cycle, the selected slave device supplies/samples the first word the MPC823e points to and asserts the BI signal with TA for the first transfer of the burst access. The MPC823e responds by terminating the burst and accessing the...
Page 324 RECEIVE DATA DO NOT BDIP ASSERTED DRIVE DATA NEGATE BDIP RETURN DATA ASSERT TA RECEIVE DATA NEGATE BURST STOP DRIVING ADDRESS AND ATTRIBUTES NEGATE BB Figure 13-10. Basic Flow Diagram Of A Burst Read Cycle MOTOROLA MPC823e REFERENCE MANUAL 13-17...
Page 325 External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA IS VALID IS VALID IS VALID IS VALID Figure 13-11. Burst-Read Cycle–32-Bit Port Size–Zero Wait State 13-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 326 A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA WAIT STATE IS VALID IS VALID IS VALID IS VALID Figure 13-12. Burst-Read Cycle–32-Bit Port Size–One Wait State MOTOROLA MPC823e REFERENCE MANUAL 13-19...
Page 327 RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA IS VALID IS VALID IS VALID IS VALID WAIT STATE Figure 13-13. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats 13-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 328 DO NOT SAMPLE BDIP ASSERTED NEXT DATA NEGATE BDIP RECEIVE DATA ASSERT TA STOP DRIVING DATA NEGATE BB NEGATE BURST STOP DRIVING ADDRESS AND ATTRIBUTES Figure 13-14. Basic Flow Diagram of a Burst Write Cycle MOTOROLA MPC823e REFERENCE MANUAL 13-21...
Page 329 External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST BDIP DATA ‘10’ Figure 13-15. Burst-Read Cycle–16-Bit Port Size–One Wait State Between Beats 13-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 330 External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT WILL DRIVE ANOTHER DATA BDIP DATA DATA DATA DATA DATA IS SAMPLED IS SAMPLED IS SAMPLED IS SAMPLED Figure 13-16. Burst-Write Cycle–32-Bit Port Size–Zero Wait States MOTOROLA MPC823e REFERENCE MANUAL 13-23...
Page 331 External Bus Interface CLKOUT A[6:27] A[28:29] N+1 MOD 4 N+2 MOD 4 N+3 MOD 4 A[30:31] RD/WR TSIZ[0:1] ‘00’ BURST BDIP DATA Figure 13-17. Burst-Inhibit Cycle–32-Bit Port Size 13-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 332: Transfer Alignment And Packaging
A 32-bit port must reside on data bus bits 0-31, a 16-bit port must reside on bits 0-15, and an 8-bit port must reside on bits 0-7. The MPC823e always tries to transfer the maximum amount of data on all bus cycles and for a word operation it always assumes that the port is 32 bits wide at the beginning of the bus cycle.
Page 333 — — — — — — — — — — — — — — — — Half-Word — — — — Word NOTE: — Denotes that a byte is not required during that read cycle. 13-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 334: Arbitration Phase-Related Signals
NOTE: — Denotes that a byte is not required during that write cycle. 13.4.6 Arbitration Phase-Related Signals The external bus design provides for a single bus master, either the MPC823e or an external device. One or more of the external devices on the bus has the capability of becoming bus master for the external bus.
Page 335: Bus Request Signal
When configured for external central arbitration, the MPC823e drives this signal when it needs bus mastership. When the internal on-chip arbiter is used, this signal is an input to the internal arbiter and must be driven by the external bus master.
Page 336: Bus Grant Signal
When configured for external central arbitration, the BG becomes an input signal to the MPC823e from the external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master.
Page 337 SIGNALS Figure 13-22. Bus Arbitration Timing Diagram At system reset, the MPC823e can be configured to use the internal bus arbiter and it will be parked on the bus. The priority of the external device relative to the internal MPC823e bus masters is programmed in the SIUMCR, as described in Section 12.12.1.1 SIU Module...
Page 338: Address Transfer Phase-Related Signals
External Bus Interface EXT OWNER BG = 0 MPC823e INTERNAL MASTER WITH HIGHER BB = T.S EXT MASTER PRIORITY THAN THE EXTERNAL DEVICE REQUESTS BUS REQUIRES THE BUS EXT MASTER BR = 1 BB = 0 RELEASE BUS IDLE MPC823e BUS WAIT...
Page 339: Address Bus
8 bits and controlled by the internal memory controller, the burst includes 16 beats. The MPC823e bus supports critical data word first for burst. The order of the wraparound goes back to the critical word. For example, assuming data 2 is the critical word: •...
Page 340: Transfer Size Signal
13.4.7.3.5 Special Transfer Start Signal. The STS signal is driven by the MPC823e when it owns the external bus. It indicates the start of a transaction on the external bus or an internal transaction in show cycle mode.
Page 341 External Bus Interface 13-34 MPC823e REFERENCE MANUAL MOTOROLA...
Page 342 External Bus Interface MOTOROLA MPC823e REFERENCE MANUAL 13-35...
Page 343: Burst Data In Progress Signal
Transfers and Section 13.4.4 The Burst Mechanism for more information. 13.4.8 Data Transfer Phase-Related Signals 13.4.8.1 DATA SIGNAL. The D[0:31] signals are driven by the MPC823e when it owns the external bus and has initiated a write transaction to a slave device. During a read transaction the D[0:31] signals are driven by the slave device.
Page 344: Protocol For Termination Signals
SLAVE 1 SLAVE 2 SLAVE 1 SLAVE 2 NEGATES NEGATES ALLOWED TO ALLOWED TO ACKNOWLEDGE ACKNOWLEDGE DRIVE DRIVE SIGNALS SIGNALS ACKNOWLEDGE ACKNOWLEDGE SIGNALS SIGNALS TURNS OFF TURNS OFF Figure 13-25. Termination Signals Protocol Timing Diagram MOTOROLA MPC823e REFERENCE MANUAL 13-37...
Page 345: Storage Reservation Protocol
External Bus Interface 13.4.10 Storage Reservation Protocol The MPC823e storage reservation protocol supports multilevel bus structure. For each local bus, storage reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation so that a PowerPC processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address.
Page 346 • Sets the reservation when that master issues a load and reserve request • Clears the reservation when some other master issues a store to the reservation address MPC823e EXTERNAL BUS E-BUS INTERFACE MASTER AT[0:3], RSV,R/W,TS lwarx A[6:31] RESERVATION LOGIC CLKOUT Figure 13-26. Reservation On Local Bus MOTOROLA MPC823e REFERENCE MANUAL 13-39...
Page 347 If the MPC823e begins a memory cycle to the previously reserved address (located in the remote bus) as a result of a stwcx instruction, one of the following conditions can occur: •...
Page 348: Exception Control Cycles
Figure 13-27. Reservation On Multilevel Bus Hierarchy 13.4.11 Exception Control Cycles The MPC823e bus architecture requires the TA signal to be asserted from an external device to indicate that the bus cycle is complete. TA is not asserted when one of the following conditions occur: •...
Page 349: Retry Signal
In the next clock cycle, a normal arbitration procedure may occur. The figure also shows that the external master did not use the bus, so the MPC823e initiates a new transfer with the same address and attributes as before. In Figure 13-29 the same situation is illustrated to show that the MPC823e is working with an external arbiter.
Page 350 External Bus Interface CLKOUT BG(OUTPUT) ALLOW EXTERNAL MASTER TO GAIN THE BUS A[6:31] RD/WR TSIZ[0:1] BURST DATA RETRY Figure 13-28. RETRY Transfer Timing–Internal Arbiter MOTOROLA MPC823e REFERENCE MANUAL 13-43...
Page 351 External Bus Interface CLKOUT BR(OUTPUT) ALLOW EXTERNAL MASTER TO GAIN THE BUS A[6:31] RD/WR TSIZ[0:1] BURST DATA RETRY Figure 13-29. RETRY Transfer Timing–External Arbiter 13-44 MPC823e REFERENCE MANUAL MOTOROLA...
Page 352 When the RETRY signal is asserted as a termination signal on the second or third data beat of the access, the MPC823e recognizes it as a transfer error acknowledgement. If a “non burst” access to a small port size device is...
Page 353 In reference to Figure 13-30, if the BI signal is asserted at the first beat of a burst, then the remaining beats of the 16-byte transfer retry are recognized as a transfer error acknowledge. Table 13-6 summarizes how the MPC823e recognizes the termination signals provided by the slave device that the initiated transfer addressed.
Page 354: Endian Modes
Motorola. Throughout the MPC823e Reference Manual , the term system refers to the devices that reside on the MPC823e bus. The MPC823e core operates in the big-endian mode of a big-endian system and in the PowerPC little-endian mode of two other configurations.
Page 355 Microprocessor Family: The Programming Environments for 32-Bit Microprocessors manual for more information. • The MPC823e internal bus signal is driven by the master that informs the system interface unit to swap and perform address demunging or leave the current access as it is.
Page 356: Little-Endian Features
Information in the Buffer Descriptors The following tables describe how to handle the little-endian program or data in the little-endian system that is built around the MPC823e for various port sizes. Table 14-3. Little-Endian Program/Data Path Between the Register and 32-Bit Memory...
Page 357 LOAD ENDIAN REGISTER CACHES FORMAT PROGRAM/DATA STORE ADDRESS CACHES ADDRESS TYPE ADDRESS Word Half-word Half-word Byte ‘a’ ‘a’ ‘a’ ‘a’ Byte ‘b’ ‘b’ ‘b’ ‘b’ Byte ‘c’ ‘c’ ‘c’ ‘c’ Byte ‘d’ ‘d’ ‘d’ ‘d’ 14-4 MPC823e REFERENCE MANUAL MOTOROLA...
Page 358: Big-Endian System Features
The endian mode must be set early in the reset routine and remain unchanged for the duration of system operation. The MPC823e core is in big-endian mode after reset. To switch between the different endian modes of operation, the core must run in serialized mode and the caches must be disabled.
Page 359: Memory Controller
Compatible with SRAM, EPROM, FEPROM, and peripherals Global (boot) chip-select available at system reset Boot chip-select support for 8-, 16-, and 32-bit devices Two clock accesses to external device Four byte write enable (WE[0:3]) signals Output enable (OE) signal MOTOROLA MPC823e REFERENCE MANUAL 15-1...
Page 360 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, 64M, 128M, 256M page banks Glueless interface to EDO, self refresh, and synchronous DRAM devices A block diagram of the memory controller is illustrated in Figure 15-1. 15-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 361 DONE WP ERROR MEMORY DATA REGISTER (MDR) MEMORY STATUS REGISTER (MSTAT) PARITY ERROR DP[0:3] MEMORY ADDRESS REGISTER (MAR) D[0:31] PARITY LOGIC MEMORY PERIODIC TIMER PRESCALE REGISTER (MPTPR) Figure 15-1. Memory Controller Block Diagram (Single UPM) MOTOROLA MPC823e REFERENCE MANUAL 15-3...
Page 362: Architecture
SRAM, Flash EPROM, and other peripherals. General-purpose chip-select signals are available on CS[0:7]. CS0 also functions as the boot chip-select signal that allows the CPU to access the boot EPROM from reset. Each chip-select allows a maximum of 30 wait states. 15-4 MPC823e REFERENCE MANUAL MOTOROLA...
Page 363 Some features are common to all eight memory banks. The full 32-bit decode is available internally, even if all 32 address bits are not visible outside the MPC823e. For external master transactions, the memory controller extends the 26-bit external address line to 32 bits and the six most-significant bits are zero.
Page 364 The memory controller provides four parity (DP[0:3]) signals, one for each data byte lane on the MPC823e system bus. The parity on the bus is only checked if the memory bank accessed in the current transaction has parity enabled. Parity checking/generation can be enabled for a specific memory bank in the base register.
Page 365: Register Model
(MAR) allows a specific address pattern to be output onto the A[6:31] signals. The memory periodic timer prescaler register (MPTPR) defines the divisor of the BRGCLK used as the memory periodic timer input clock. MOTOROLA MPC823e REFERENCE MANUAL 15-7...
Page 366 It also asserts the TEA signal and sets the corresponding DPB bit in the TESR, which is described in Section 12.12.1.4 Transfer Error Status Register. The memory controller asserts an internal transfer error signal when a parity error occurs (if enabled). 15-8 MPC823e REFERENCE MANUAL MOTOROLA...
Page 367: Register Descriptions
(IMMR & 0xFFFF0000) + 0x100 (BR0), 0x108 (BR1), 0x110, (BR2), 0x118 (BR3), 0x120 (BR4), 0x128 (BR5), 0x130 (BR6), 0x138 (BR7) FIELD PARE RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0x102 (BR0), 0x10A (BR1), 0x112, (BR2), 0x11A (BR3), 0x122 (BR4), 0x12A (BR5), 0x132 (BR6), 0x13A (BR7) MOTOROLA MPC823e REFERENCE MANUAL 15-9...
Page 368 MSTAT register if you try to write to this memory bank. MS—Machine Select This field specifies the machine that is selected for memory operations handling. 00 = GPCM. 01 = Reserved. 10 = UPMA. 11 = UPMB. 15-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 369 GPCM parameters. After reset, OR0 is referred to as the Boot OR0 and it has a special functionality until the first write to OR0. BOOT OR0 FIELD RESET ADDR (IMMR & 0xFFFF0000) + 0x104 CSNT/ FIELD ACS/G5LA,G5LS SETA TRLX EHTR RESET ADDR (IMMR & 0xFFFF0000) + 0x106 MOTOROLA MPC823e REFERENCE MANUAL 15-11...
Page 370 1 = Address pins reflect the address requested by the internal master multiplexed according to the AMA field (if UPMA is selected to control the memory access) or the AMB field (if UPMB is selected). 15-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 371 It is one of the parameters that control the cycle’s length. The total cycle length is controlled by this parameter and the TRLX field. Refer to Table 15-2 (page 15-28) for the total number of cycles. MOTOROLA MPC823e REFERENCE MANUAL 15-13...
Page 372 GPCM is selected to handle the memory access that was initiated to this memory region. Refer to Table 15-2 (page 15-28) for more information. 0 = Timing is defined by the GPCM. 1 = Relaxed timing is defined by the GPCM. 15-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 373 When this bit is set it indicates that a parity error was detected during a Bank 4 read cycle initiated by the memory controller. PER5—Parity Error Bank 5 When this bit is set it indicates that a parity error was detected during a Bank 5 read cycle initiated by the memory controller. MOTOROLA MPC823e REFERENCE MANUAL 15-15...
Page 374 Note: If the bus monitor is disabled and the write-protect error occurs, TEA assertion will not occur. See Section 12.12.1.4 Transfer Error Status Register for more information. Bits 9–15—Reserved These bits are reserved and must be set to 0. 15-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 375 These bits are reserved and must be set to 0. UM—User Machine This bit selects the user-programmable machine for this command. 0 = UPMA. 1 = UPMB. Bits 9–15—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 15-17...
Page 376 1111 = The loop is executed 15 times. 0000 = The loop is executed 16 times. MAD—Memory Array Index This field specifies an index to one of 64 RAM words in the RAM array for command execution. 15-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 377 32, and a DFBRG field that is equal to 0, then the PTA value must be (25 × 15.6) / (2 × 32× 1) = 12. If you want to perform more than one refresh 2×0 per service, use the TLFA field. MOTOROLA MPC823e REFERENCE MANUAL 15-19...
Page 378 001 = A11 is selected. 010 = A10 is selected. 011 = A9 is selected. 100 = A8 is selected. 101 = A7 is selected. 110 = A6 is selected. 111 = A5 is selected. 15-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 379 1100 = The loop is executed 12 times. 1101 = The loop is executed 13 times. 1110 = The loop is executed 14 times. 1111 = The loop is executed 15 times. 0000 = The loop is executed 16 times. MOTOROLA MPC823e REFERENCE MANUAL 15-21...
Page 380 UPM, the refreshes will progress through each one. For example, if you have three chip-selects using UPMA, you would need to set the periodic timer A period to one-third the normal refresh. 15-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 381 UPMB, assuming they have the same timing. The maximum disable period is four clock cycles. When switching to a different bank that requires more than four clock cycles, you must add more UPM RAM word to meet your time requirement. MOTOROLA MPC823e REFERENCE MANUAL 15-23...
Page 382 1100 = The loop is executed 12 times. 1101 = The loop is executed 13 times. 1110 = The loop is executed 14 times. 1111 = The loop is executed 15 times. 0000 = The loop is executed 16 times. 15-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 383 1100 = The loop is executed 12 times. 1101 = The loop is executed 13 times. 1110 = The loop is executed 14 times. 1111 = The loop is executed 15 times. 0000 = The loop is executed 16 times. MOTOROLA MPC823e REFERENCE MANUAL 15-25...
Page 384 (IMMR & 0xFFFF0000) + 0x166 MA—Memory Address This field contains a 32-bit address to be output on the address bus if the AMX field is equal to 11. Refer to Section 15.5.4 The RAM Array for more information. 15-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 385 15.4 THE GENERAL-PURPOSE CHIP-SELECT MACHINE The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the MPC823e, SRAM, EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains three basic register groups that you can use to configure it—base registers 0–7, option registers 0–7, and the memory status register.
Page 386 Write — (1+1/4)*Clock 1+3/4*Clock 3/4*Clock 1+1/2*Clock 4+2*SCY (1+1/2)*Clock 1+3/4*Clock 3/4*Clock 3/4*Clock -1/4*Clock 1/4*Clock 3+2*SCY 1+3/8*Clock (1+1/4)*Clock 1+3/4*Clock 3/4*Clock 1+3/8*Clock 4+2*SCY (1+1/2)*Clock 1+3/4*Clock 3/4*Clock NOTE: SCY is the number of wait cycles from the option register. 15-28 MPC823e REFERENCE MANUAL MOTOROLA...
Page 387 DATA Figure 15-5. GPCM Memory Device Interface Figure 15-5 illustrates a basic connection between the MPC823e and a “static” memory device. In this case, the CSx signal is connected directly to the CE signal of the memory device. The WEx signals are connected to the respective W signal of the memory device in which each WEx signal corresponds to a different data byte.
Page 388 CSNT bit of the ORx register. The CSx signal is generated when the ACS field in the corresponding ORx register is set to ‘00’. CLOCK ADDRESS CSNT = 1 DATA Figure 15-6. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, and TRLX = 0) 15-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 389 Figure 15-8 illustrates the CSx signal as defined by the setup time required between the address lines and the CE signal. The MPC823e memory controller allows you to specify the CSx signal to meet this requirement using the ACS field of the option register.
Page 390 The TRLX field in the option register is provided for memory systems that require more relaxed timing between signals. When TRLX is set and the ACS field is not equal to 00, an additional cycle between the address and strobes is inserted by the MPC823e memory controller, as shown in Figure 15-9.
Page 391 Memory Controller CLOCK ADDRESS ACS = 10 ACS = 11 DATA Figure 15-10. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 10 or 11, SCY = 0, CSNT = 0, and TRLX = 1) CLOCK ADDRESS ACS = 10 ACS = 11 DATA Figure 15-11.
Page 392 CLOCK ADDRESS DATA Figure 15-12. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 00, SCY = 0, CSNT = 1, and TRLX = 1) 15.4.1.1 PROGRAMMABLE WAIT STATE CONFIGURATION. The general-purpose chip-select machine supports internal TA signal generation. It allows “fast” accesses to external memory through an internal bus master or it allows a maximum 17-clock access.
Page 393 Memory Controller CLOCK ADDRESS HOLD TIME DATA Figure 15-13. GPCM Read Followed By Write (EHTR = 0) CLOCK ADDRESS HOLD TIME DATA LONG HOLD TIME ALLOWED Figure 15-14. GPCM Write Followed By Read (EHTR = 1) MOTOROLA MPC823e REFERENCE MANUAL 15-35...
Page 394 LONG HOLD TIME ALLOWED Figure 15-15. GPCM Read Followed By Read From Different Banks (EHTR = 1) CLOCK ADDRESS HOLD TIME DATA Figure 15-16. GPCM Read Followed By Read From Same Bank (EHTR = 1) 15-36 MPC823e REFERENCE MANUAL MOTOROLA...
Page 395 ROM before system initialization occurs. The CS0 signal is the boot chip-select output and its operation differs from the other external chip-select outputs on system reset. When the MPC823e internal core begins accessing memory at system reset, CS0 is asserted for every address, unless an internal register is accessed.
Page 396 Memory Controller 15.4.1.4 SRAM INTERFACE. Figure 15-17 illustrates a simple connection between an SRAM device and the MPC823e. MEMORY 32-BIT WIDE SRAM 128K GPL_x1 / OE A[15:29] ADDRESS D[0:31] DATA Figure 15-17. GPCM to SRAM Configuration 15.4.1.5 EXTERNAL ASYNCHRONOUS MASTER SUPPORT. Figure 15-18 illustrates the basic interface between an asynchronous external master and the GPCM to allow connection to “static RAM”...
Page 397 Memory Access Timing (TRLX = 0) When an external asynchronous master performs an access to a memory device via the general-purpose chip-select machine in the memory controller, the CSNT bit in the option register is configured as “don’t care”. MOTOROLA MPC823e REFERENCE MANUAL 15-39...
Page 398 WAEN bit set, the external UPWAITx signal is sampled and synchronized by the memory controller and the current request is frozen. The signal timing generator will load the RAM word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. 15-40 MPC823e REFERENCE MANUAL MOTOROLA...
Page 399 Software requests, however, can point to any of the 64 UPM RAM entries. READ SINGLE BEAT REQUEST BURST READ REQUEST ARRAY INDEX GENERATOR WRITE SINGLE BEAT REQUEST RAM ARRAY BURST WRITE REQUEST WORDS PERIODIC TIMER REQUEST EXCEPTION CONDITION Figure 15-21. RAM Array Indexing MOTOROLA MPC823e REFERENCE MANUAL 15-41...
Page 400 UPM, the refreshes will progress through each one. For example, if you have three chip-selects using UPMA, you would need to set the periodic timer A period to one-third the normal refresh. 15-42 MPC823e REFERENCE MANUAL MOTOROLA...
Page 401 15.5.1.4 EXCEPTION REQUESTS. When an access to a memory device is initiated by the MPC823e under UPM control, the external device may assert a TEA, SRESET, or HRESET signal. The UPM provides a mechanism that allows you to handle the memory control signals to meet the timing requirements of the device without losing data.
Page 402 (if specified in the RAM array) at any edge of GCLK1 and GCLK2, plus a propagation delay. SYSTEM CLOCK CLKOUT GCLK1 GCLK2 CLOCK PHASE Figure 15-23. UPM Clock Scheme One (Division Factor = 1) 15-44 MPC823e REFERENCE MANUAL MOTOROLA...
Page 403 3 of the previous clock cycle. It determines the value of the CST1–4, G1T3, G1T4, G2T3, and G2T4 bits, which specifies the timing of chip-selects, byte-selects, and GPLx signals based on any edge of GCLK1 or GCLK2. MOTOROLA MPC823e REFERENCE MANUAL 15-45...
Page 404 CST1 CST2 CST3 GPL1 G1T4 G1T3 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G2T3 CLOCK PHASE RAM WORD 1 RAM WORD 2 Figure 15-25. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) 15-46 MPC823e REFERENCE MANUAL MOTOROLA...
Page 405 CST4 CST2 CST3 GPL1 G1T4 G1T3 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G2T3 CLOCK PHASE RAM WORD 1 RAM WORD 2 Figure 15-26. UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) MOTOROLA MPC823e REFERENCE MANUAL 15-47...
Page 406: The Ram Array
Figure 15-27. The selected bank is one of eight banks that matches the current address. The signal generation shown at the bottom part of the figure are outputs of the UPM and not direct signal outputs of the MPC823e. 32 BITS WIDE...
Page 407 This bit defines the state of the CSx signal during clock phase 3. 0 = The CSx signal is asserted at the rising edge of GCLK2. 1 = The CSx signal is negated at the rising edge of GCLK2. MOTOROLA MPC823e REFERENCE MANUAL 15-49...
Page 408 11 = The GPL0 signal is negated at the trailing edge of GCLK2. 00 = The GPL0 signal is driven at the trailing edge of GCLK2 as defined in the G0CLx field of the MxMR. 15-50 MPC823e REFERENCE MANUAL MOTOROLA...
Page 409 This bit defines the state of the GPL3 signal during clock phase 4. 0 = The GPL3 signal is asserted at the trailing edge of GCLK1. 1 = The GPL3 signal is negated at the trailing edge of GCLK1. MOTOROLA MPC823e REFERENCE MANUAL 15-51...
Page 410 0 = The value of the GPL5 signal at the trailing edge of GCLK1 will be 0. 1 = The value of the GPL5 signal at the trailing edge of GCLK1 will be 1. Bits 22 and 23—Reserved These bits are reserved and must be set to 0. 15-52 MPC823e REFERENCE MANUAL MOTOROLA...
Page 411 — If the accessed bank has an 8-bit port size, the value of the A[28:31] signals are incremented by 1. Note: The value of the NA bit is only relevant when the UPM serves a burst-read or burst-write request. Under other patterns this bit is reserved. MOTOROLA MPC823e REFERENCE MANUAL 15-53...
Page 412 REQUEST TO BE SERVICED UPM START ADDRESS Read Single Beat Cycle (RSS) 0x’00 Read Burst Cycle (RBS) 0x’08 Write Single Beat Cycle (WSS) 0x’18 Write Burst Cycle (WBS) 0x’20 Periodic Timer Request (PTS) 0x’30 Exception (EXS) 0x’3C 15-54 MPC823e REFERENCE MANUAL MOTOROLA...
Page 413 UPM, the refreshes will progress through each one. For example, if you have three chip-selects using UPMA, you would need to set the periodic timer A period to one-third the normal refresh. MOTOROLA MPC823e REFERENCE MANUAL 15-55...
Page 414 Figure 15-29 illustrates how the BSx signals are controlled by the user-programmable machines. BANK SELECTED A[30:31] PS IN BRx TSIZx MS IN BRx UPMA BYTE- SELECT LOGIC UPMB Figure 15-29. BSx Signal Selection 15-56 MPC823e REFERENCE MANUAL MOTOROLA...
Page 415 BSx signals are only determined by the port size of the bank. Table 15-5. Enabling Byte-Selects TRANSFER TSIZx ADDRESS 32-BIT PORT SIZE 16-BIT PORT SIZE 8-BIT PORT SIZE SIZE A30 A31 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 Byte Half-Word Word MOTOROLA MPC823e REFERENCE MANUAL 15-57...
Page 416 MxMR. To use this feature, you must set the G0H and G0L fields in the RAM word. For example, if you have a SIMM with multiple banks, this address line can be used to switch between banks. 15-58 MPC823e REFERENCE MANUAL MOTOROLA...
Page 417 HRESET signal. An exception occurs when one of these signals is asserted by an external device and the MPC823e begins closing the memory cycle transfer. When an exception is recognized and the EXEN bit is set in the RAM word, the next RAM word will branch to the special exception start address (EXS).
Page 418 DRAM modules. Figure 15-31 illustrates address multiplex timing. CLKOUT/GCLK2 GCLK1 UPPER ADDRESS LOWER ADDRESS A[0:31] ADDRESS CONTROLLED ADDRESS CONTROLLED BY AMX BY SAM RAM WORD 1 RAM WORD 2 Figure 15-31. Address Multiplex Timing Table 15-7. Address Multiplexing PINS AMA/AMB SIGNALS 15-60 MPC823e REFERENCE MANUAL MOTOROLA...
Page 419 A16 - A31 A21 - A31 A20 - A31 A19 - A31 A18 - A31 A17 - A31 A20 - A31 A19 - A31 A18 - A31 128M A17 - A31 256M A16 - A31 MOTOROLA MPC823e REFERENCE MANUAL 15-61...
Page 420 A16 - A30 A20 - A30 A19 - A30 A18 - A30 A17 - A30 A19 - A30 A18 - A30 128M A17 - A30 256M A16 - A30 128M A18 - A30 256M A17 - A30 15-62 MPC823e REFERENCE MANUAL MOTOROLA...
Page 421 A19 - A29 A18 - A29 A17 - A29 A16 - A29 A19 - A29 A18 - A29 A17 - A29 A18 - A29 128M A17 - A29 256M A16 - A29 256M A17 - A29 MOTOROLA MPC823e REFERENCE MANUAL 15-63...
Page 422 (if any) is serviced immediately in the external memory transactions. If the disable timer is activated, the bus will be idle for a number of clock cycles, as specified in the DSx field of the MxMR. 15-64 MPC823e REFERENCE MANUAL MOTOROLA...
Page 423 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 GPL1 WAEN UPWAITx RAM WORD N RAM WORD N+1 RAM WORD N+2 WAIT WAIT RAM WORD N+3 Figure 15-33. Wait Mechanism Timing For Internal and External Synchronous Masters MOTOROLA MPC823e REFERENCE MANUAL 15-65...
Page 424 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 GPL1 WAEN RAM WORD N RAM WORD N+1 RAM WORD N+2 WAIT WAIT RAM WORD N+3 Figure 15-34. Wait Mechanism Timing For An External Asynchronous Master 15-66 MPC823e REFERENCE MANUAL MOTOROLA...
Page 425 CPU will sample the data only after the negation of the UPWAITx signal. • The External TA Solution—The CPU generates a read access from the slow device. When it is ready, the device is responsible for generating the synchronous TA signal. MOTOROLA MPC823e REFERENCE MANUAL 15-67...
Page 426 TA signal are negated with AS pin negation. If the AEME bit is cleared, the memory controller is bypassed and the external asynchronous master must provide control signals to the slave device. In this mode, the AS pin of the MPC823e is not available as an input. See Figure 15-36 for details.
Page 427 On subsequent clock cycles, the behavior of the A[28:20] pins depends on the configuration of the UPM. ADDRESS MEMORY MATCH DEVICE ACCESS COMPARE CLKOUT A[6:27] A[28:31] BURST TSIZEx DATA Figure 15-35. Synchronous External Master Access MOTOROLA MPC823e REFERENCE MANUAL 15-69...
Page 428 G5LA bit of the option register to select the active GPL_x5 signal. G5LS only applies to memory requests and not RAM words executed by internal/external software, exception, or memory periodic timer requests. 15-70 MPC823e REFERENCE MANUAL MOTOROLA...
Page 429 GCLK2 in the current UPM cycle. GPL_A5 is driven low at the falling edge of GCLK1 in the current UPM cycle. GPL_A5 is driven high at the falling edge of GCLK1 in the current UPM cycle. MOTOROLA MPC823e REFERENCE MANUAL 15-71...
Page 430 Memory Controller 15.6.1 External Master Examples A synchronous example interconnection in which an external master and the MPC823e can both share access to a DRAM bank is illustrated in Figure 15-37. Notice that CS1, UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses. To perform burst accesses initiated by the external master or MPC823e using this configuration, the A[28:30] signals are connected to the multiplexer controlled by GPL_A5.
Page 431 (Bit 26) amx1 (Bit 27) (Bit 28) (Bit 29) todt (Bit 30) last (Bit 31) RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 15-38. Synchronous External Master–Burst Read Access To Page Mode DRAM MOTOROLA MPC823e REFERENCE MANUAL 15-73...
Page 432 Memory Controller An asynchronous example interconnection in which an external master and the MPC823e can both share access to a DRAM bank is illustrated in Figure 15-39. Notice that CS1, UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses.
Page 433 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 WAIT WAIT RSS+2 Figure 15-40. Asynchronous External Master Timing Example MOTOROLA MPC823e REFERENCE MANUAL 15-75...
Page 434 Figure 15-41. Page Mode DRAM Interface Connection Follow these steps to configure a system for page mode DRAM: 1. Determine the system architecture, which includes the MPC823e and the memory system as shown in the example in Figure 15-41. 2. Use the blank worksheet (Figure 15-58) to draw the timing diagrams for all the memory cycles associated with your architecture.
Page 435 Selects Two Disable Timer Clock Cycles GPLA4DIS MAMR Disables the UPWAITA Signal RLFA MAMR 0011 Selects Three Loop Iterations for Read WLFA MAMR 0011 Selects Three Loop Iterations for Write Selects Column Address on First Cycle Supports Burst Accesses MOTOROLA MPC823e REFERENCE MANUAL 15-77...
Page 436 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 15-42. Single Beat Read Access To Page Mode DRAM 15-78 MPC823e REFERENCE MANUAL MOTOROLA...
Page 437 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 Figure 15-43. Single Beat Write Access To Page Mode DRAM MOTOROLA MPC823e REFERENCE MANUAL 15-79...
Page 438 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 15-44. Burst Read Access To Page Mode DRAM (No LOOP) 15-80 MPC823e REFERENCE MANUAL MOTOROLA...
Page 439 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 15-45. Burst Read Access To Page Mode DRAM (LOOP) MOTOROLA MPC823e REFERENCE MANUAL 15-81...
Page 440 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 15-46. Burst Write Access To Page Mode DRAM (No LOOP) 15-82 MPC823e REFERENCE MANUAL MOTOROLA...
Page 441 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 Figure 15-47. Burst Write Access To Page Mode DRAM (Loop) MOTOROLA MPC823e REFERENCE MANUAL 15-83...
Page 442 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 15-48. Refresh Cycle (CAS Before RAS) To Page Mode DRAM 15-84 MPC823e REFERENCE MANUAL MOTOROLA...
Page 443 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 15-49. Exception Cycle MOTOROLA MPC823e REFERENCE MANUAL 15-85...
Page 444 DRAM access time. When a 16-bit port size memory is connected, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles. 15-86 MPC823e REFERENCE MANUAL MOTOROLA...
Page 445 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 15-50. Optimized DRAM Burst Read Access MOTOROLA MPC823e REFERENCE MANUAL 15-87...
Page 446 Figure 15-51. EDO DRAM Interface Connection Follow these steps to configure a system for EDO DRAM: 1. Determine the system architecture, which includes the MPC823e and the memory system as shown in the example in Figure 15-52. 2. Use the blank worksheet (Figure 15-58) to draw the timing diagrams for all the memory cycles associated with your architecture.
Page 447 Selects Two Disable Timer Clock Cycles GPLB4DIS MBMR Disables the UPWAITB Signal RLFB MBMR 0011 Selects Three Loop Iterations for Read WLFB MBMR 0011 Selects Three Loop Iterations for Write Selects Column Address on First Cycle Supports Burst Accesses MOTOROLA MPC823e REFERENCE MANUAL 15-89...
Page 448 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 15-52. EDO DRAM Single Beat Read Access 15-90 MPC823e REFERENCE MANUAL MOTOROLA...
Page 449 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 WSS+3 Figure 15-53. EDO DRAM Single Beat Write Access MOTOROLA MPC823e REFERENCE MANUAL 15-91...
Page 450 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 15-54. EDO DRAM Burst Read Access 15-92 MPC823e REFERENCE MANUAL MOTOROLA...
Page 451 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 15-55. EDO DRAM Burst Write Access MOTOROLA MPC823e REFERENCE MANUAL 15-93...
Page 452 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 15-56. EDO DRAM Refresh Cycle (CAS Before RAS) 15-94 MPC823e REFERENCE MANUAL MOTOROLA...
Page 453 Bit 21 Bit 22 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 15-57. EDO DRAM Exception Cycle MOTOROLA MPC823e REFERENCE MANUAL 15-95...
Page 454 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 xxS+1 xxS+2 xxS+3 xxS+4 xx+5 xxS+6 xxS+7 xxS+8 Figure 15-58. Blank Worksheet for a UPM 15-96 MPC823e REFERENCE MANUAL MOTOROLA...
Page 455 SECTION 16 COMMUNICATION PROCESSOR MODULE The MPC823e communication processor module (CPM) provides a flexible and integrated approach to communication-intensive environments. To reduce system frequency and save power, the communication processor module has its own independent RISC microcontroller that is optimized and tuned to handle serial communications. The communication processor module offloads the core in the following ways: •...
Page 456 Infra-red protocols (SCC2 only) Transparent protocol Ethernet protocol • Universal serial bus controller • Serial management controllers UART protocol Transparent protocol GCI protocol • Serial peripheral interface • I C bus controller • General-purpose parallel interface ports 16-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 457 BUS INTERFACE SDMA CONTROLLER INTERNAL BUS RISC TIMERS MICROCONTROLLER SEQUENCER DUAL-PORT PARALLEL I/O PORTS REGISTER FILE BAUD RATE GENERATORS PERIPHERAL BUS SCC3 SMC1 SMC2 SCC2 SERIAL INTERFACE AND TIME-SLOT ASSIGNER Figure 16-1. CPM Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 16-3...
Page 458 Communication Processor Module The MPC823e offers an extremely flexible set of communication capabilities. The remainder of this section discusses all the possible ways you can configure the communication processor module. Figure 16-2 illustrates a sample configuration for a personal digital assistant (PDA) application that supports various communication links and protocols.
Page 459 • DMA Bursts Serial Data to External Memory INSTRUCTION PROCESSING STORAGE UNITS MULTIPLY DECODER ACCUMULATE REGISTER CYCLIC PERIPHERAL REDUNDANCY FILE CHECK INTERFACE DEVELOPMENT ARITHMETIC SEQUENCER SUPPORT LOGIC UNIT SCHEDULER PERIPHERAL DUAL-PORT RAM SERVICE REQUESTS Figure 16-3. RISC Microcontroller Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 16-5...
Page 460 7. USB Transmission (TX) 8. SCC2 RX 9. SCC2 TX 10. SCC3 RX 11. SCC3 TX 12. IDMA DREQ1 (option 2) 13. IDMA DREQ2 (option 2) 14. SMC1 RX 15. SMC1 TX 16. SMC2 RX 17. SMC2 TX 16-6 MPC823e REFERENCE MANUAL MOTOROLA...
Page 461 You can execute microcode from the dual-port RAM or on-chip ROM. This flexibility not only allows Motorola to add more protocols or enhancements to the MPC823e, but it also allows you to obtain binary microcode. Refer to Table 16-1 for more information.
Page 462 11 = Reserved. EIE—External Interrupt Enable Configure this bit as instructed in the download process of a Motorola-supplied RAM microcode package. This bit is also used by IDMA channel 1 to enable single-buffer mode, as described in Section 16.6.3.11.4 Single-Buffer Burst Fly-By Mode .
Page 463 Communication Processor Module SCD—Scheduler Configuration Configure this bit as instructed in the download process of a Motorola-supplied RAM microcode package. 0 = Normal operation. 1 = Alternate configuration of the scheduler. ERAM—Enable RAM Microcode Configure this field as instructed in the download process of a Motorola-supplied RAM microcode package.
Page 464 This field is set by the core to define the peripheral I/O channel that the command is applied to. Some peripherals share channel number encodings if their commands are mutually exclusive. See Table 16-2 for more information. Bits 12–14—Reserved These bits are reserved and must be set to 0. 16-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 465 — — INIT INIT — IDMA IDMA 1110 — — — — — — — — — — — 1111 — — — — — — — — — — Command NOTE: — = Reserved. MOTOROLA MPC823e REFERENCE MANUAL 16-11...
Page 466 • SET GROUP ADDRESS—The set group address command sets a hash table bit for the Ethernet logical group address recognition function. • GCI ABORT REQUEST—The GCI abort request command causes the MPC823e receiver to send an abort request on the A bit of the GCI bus.
Page 467 Communication Processor Module • GCI TIMEOUT—The GCI timeout command causes the MPC823e transmitter to send an abort request on the E bit of the GCI bus. • USB—The USB commands have the same opcode. See Section 16.10 Universal Serial Bus Controller for a more detailed description.
Page 468 DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x3800 BD / DATA DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x3A00 BD / DATA / µCODE DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x3C00 PARAMETER RAM Figure 16-5. Dual-Port RAM Memory Map 16-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 469 • To store the data from the serial channels. This is optional because data can also be stored in external memory. • To store the RAM microcode for the RISC microcontroller. This feature allows Motorola to add protocols in the future.
Page 470 IMMR + 0x3F00 DPRAM_Base+ 0x1f00 Reserved DPRAM_Base+ 0x1f7f DPRAM_Base+ 0x1f80 SMC2 DPRAM_Base+ 0x1fbf DPRAM_Base+ 0x1fc0 DSP2 DPRAM_Base+ 0x1fff NOTE: DPRAM_Base = (IMMR & 0xFFFF0000) + 0x2000. * 0x1da3 for Ethernet. † 0x1ea3 for SCC3 Ethernet. 16-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 471 The timer tables are configured in the RCCR, the timer table parameter RAM, the SET TIMER command that is issued to the CPCR, the timer event register, and the timer mask register. MOTOROLA MPC823e REFERENCE MANUAL 16-17...
Page 472 DUAL-PORT RAM 16 RISC TIMER TABLE ENTRIES (UP TO 64 BYTES) INDEX POINTER TIMER PARAMETER RAM IMMR + 3DB0 TIMERBASE TM_BASE RISC TIMER TABLE PARAMETER RAM (14 BYTES) Figure 16-6. RISC Timer Table RAM Usage 16-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 473 • TM_PTR—This index pointer is used exclusively by the RISC microcontroller to point to the next entry to be executed in the timer table. You must not modify this pointer. MOTOROLA MPC823e REFERENCE MANUAL 16-19...
Page 474 TMR13 TMR12 TMR11 TMR10 TMR9 TMR8 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 RESET ADDR (IMMR & 0xFFFF0000) + 0x3DB6 TMR0–15—Timer 0–15 0 = No effect. 1 = Clears a bit in this register. 16-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 475 It is updated if the microcontroller’s internal timer is enabled, regardless of whether any of the 16 timers are enabled, and it can be used to track the number of ticks the microcontroller receives and responds to. MOTOROLA MPC823e REFERENCE MANUAL 16-21...
Page 476 PORT B PIN 0 and 1 PB23 2 and 3 PB22 4 and 5 Not Available 6 and 7 Not Available 8 and 9 PB19 10 and 11 PB18 12 and 13 PB17 14 and 15 PB16 16-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 477 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 RESET ADDR (IMMR & 0xFFFF0000) + 0x9DA TMR0–15—Timer 0–15 0 = Masks the corresponding interrupt in the RTER. 1 = Enables the corresponding interrupt in the RTER. MOTOROLA MPC823e REFERENCE MANUAL 16-23...
Page 478 This enables RISC timer 0 to timeout after 3,814 (decimal) ticks. The timer automatically restarts after it times out. 8. Write 0x0851 to the CPCR to issue the SET TIMER command. 9. Set the TIME bit in the RCCR to operate the RISC timer. 16-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 479 96% utilization level. Note: The general-purpose timers are up-counters, but the RISC microcontroller timers are down-counters. You must take this under consideration when comparing timer counts. MOTOROLA MPC823e REFERENCE MANUAL 16-25...
Page 480 (FIR) filters with or without adaptive equalization, data compression, and scrambling. These are written in software on the MPC823e and do not require your system to have a separate DSP processor, which would cost you more and consume more power.
Page 481 Figure 16-8, the pointer to the transmit (TX) chain must be written into the FDBASE field of the DSP2 parameter RAM and the pointer to the receive (RX) chain must be written into DSP1. MOTOROLA MPC823e REFERENCE MANUAL 16-27...
Page 482 16-bit half-words—one word for the imaginary component and one for the real component as shown in Figure 16-8. They must be scaled to fit in the -1 and +1 range. FIELD REAL FRACTION FIELD IMAGINARY FRACTION FIELD REAL FRACTION 16-28 MPC823e REFERENCE MANUAL MOTOROLA...
Page 483 PARAMETER 7 S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1 and 4–10—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-29...
Page 484 The FDBASE index pointer defines the place in system memory for the function descriptor chain to start. It must be 16-byte aligned. Also, the FDBASE index pointer must be initialized before the INIT_DSP command is issued. See Table 16-7 for DSP parameter RAM memory map details. 16-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 485 DSTATUS—Current Function Descriptor Status This bit defines the current status of the current function descriptor. It is only used by the RISC microcontroller, so you do not need to modify it in any way. MOTOROLA MPC823e REFERENCE MANUAL 16-31...
Page 486 (CPCR) and their functionality is described in Table 16-6. • INIT DSP CHAIN—Deactivates the corresponding chain. The function descriptor pointer is initialized to the starting address provided in the function descriptor table. • START DSP CHAIN—Activates the corresponding chain. 16-32 MPC823e REFERENCE MANUAL MOTOROLA...
Page 487 This bit is set when the chain 2 function finishes executing. However, the I bit must be set in the function descriptor. DSP1—DSP Chain 1 Receiver Interrupt (DSP function) This bit is set when the chain 1 function finishes executing. However, the I bit must be set in the function descriptor. MOTOROLA MPC823e REFERENCE MANUAL 16-33...
Page 488 0 = Disable the DSP chain 1 interrupt. 1 = Enable the DSP chain 1 interrupt. DSP2—DSP Chain 2 Transmitter Interrupt (DSP function) 0 = Disable the DSP chain 2 interrupt. 1 = Enable the DSP chain 2 interrupt. 16-34 MPC823e REFERENCE MANUAL MOTOROLA...
Page 489 FIR2 writes the three results into the output buffer, which is also the modulation input buffer. Modulation is accomplished by invoking MOD with a three-iteration count. The input pointer is autoincremented with each iteration. MOTOROLA MPC823e REFERENCE MANUAL 16-35...
Page 490 () U8 i; S32 termrnd; extern S16 mult(S16 p1, S16 p2); /* in-line invocation */ i=0; while (i<SAMPLE_PER_T) { sigout[i]= mult(sn1800[REAL][cosindx], modbuf[REAL][i]) - mult(sn1800[IMAG][cosindx], modbuf[IMAG][i]); cosindx++; if (cosindx==SIN1800TBL_LEN)cosindx=0; i++; void main () tx_filter(); modulator(); 16-36 MPC823e REFERENCE MANUAL MOTOROLA...
Page 491 MODULATION FD MOD TABLE PTR OPCODE = MOD # OF ITTERATIONS MOD TABLE SIZE OUTPUT BUFFER TABLE MPTR IN BUFFER SIZE XYPTR INPUT POINTER OUT BUFFER SIZE OUTPUT POINTER Figure 16-11. Core and CPM Implementation MOTOROLA MPC823e REFERENCE MANUAL 16-37...
Page 492 • FIR3—Finite impulse response 3 • FIR5—Finite impulse response 5 • FIR6—Finite impulse response 6 • IIR—Infinite impulse response • MOD—Modulation • DEMOD—Demodulation • LMS1—Least mean squared 1 • LMS2—Least mean squared 2 • WADD—Weighted vector addition 16-38 MPC823e REFERENCE MANUAL MOTOROLA...
Page 493 COEFFICIENTS INPUT SAMPLES OUTPUT C(0) C(1) C(2) x(N-k+1) Y(N-k+1) C(k-1) x(N-2) x(N-1) x(N) Y(N-2) Y(N-1) Y(N) 2K bytes M + 1 bytes N + 1 bytes Figure 16-13. FIR1 Coefficients and Sample Data Buffers MOTOROLA MPC823e REFERENCE MANUAL 16-39...
Page 494 0 = The X (input) data pointer is incremented (Modulo M+1) by the number of samples specified in the INDEX field after the last iteration. 1 = The X data pointer is incremented (Modulo M+1) by the number of samples specified in the INDEX field after each iteration. 16-40 MPC823e REFERENCE MANUAL MOTOROLA...
Page 495 16.3.4.1.4 Application Example. The FIR1 is used in decimation and RX interpolation. For example, the following function descriptor structure can be used to implement a 2 to 1 decimation. 00001 OFFSET + 0 I=3 (THREE ITERATIONS) OFFSET + 2 MOTOROLA MPC823e REFERENCE MANUAL 16-41...
Page 496 The output buffer is a cyclic buffer containing N+1 bytes. Each output is two 16-bit half-words (real and imaginary components). The new output is stored in the address that follows the previous output. 16-42 MPC823e REFERENCE MANUAL MOTOROLA...
Page 497 OFFSET + C RESERVED OFFSET + E The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. MOTOROLA MPC823e REFERENCE MANUAL 16-43...
Page 498 0 = The coefficients pointer is not preset after each iteration. 1 = The coefficients pointer is preset after each iteration to CBASE pointer. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. 16-44 MPC823e REFERENCE MANUAL MOTOROLA...
Page 499 16.3.4.2.4 Application Example. The FIR2 function is used in the TX and RX filters. For example, the following function descriptor structure can be used to implement the TX filter. 00010 OFFSET + 0 I=3 (THREE ITERATIONS) OFFSET + 2 MOTOROLA MPC823e REFERENCE MANUAL 16-45...
Page 500 Y n ( ) C p ( )X n p   Real –     C(2) – ∑ Y n ( ) C p ( )X n p – C(K-1) Figure 16-16. FIR2 Implementation Example 16-46 MPC823e REFERENCE MANUAL MOTOROLA...
Page 501 16.3.4.3.2 FIR3 Function Descriptor. The FIR3 function descriptor bit table is described below. IALL INDEX OPCODE OFFSET + 0 OFFSET + 2 OFFSET + 4 CBASE OFFSET + 6 OFFSET + 8 XYPTR OFFSET + A OFFSET + C RESERVED OFFSET + E MOTOROLA MPC823e REFERENCE MANUAL 16-47...
Page 502 0 = The coefficients pointer is not preset after each iteration. 1 = The coefficients pointer is preset after each iteration to the CBASE pointer. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. 16-48 MPC823e REFERENCE MANUAL MOTOROLA...
Page 503 16.3.4.3.4 Application Example. The FIR3 with the real output is used in echo cancellation and the one with the complex output is used in the equalizer. 00011 OFFSET + 0 I=3 (THREE ITERATIONS) OFFSET + 2 MOTOROLA MPC823e REFERENCE MANUAL 16-49...
Page 504 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample. The output buffer is a cyclic buffer that contains N+1 bytes and the new output is stored in the address that follows the previous output. 16-50 MPC823e REFERENCE MANUAL MOTOROLA...
Page 505 OFFSET + C RESERVED OFFSET + E The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. MOTOROLA MPC823e REFERENCE MANUAL 16-51...
Page 506 0 = The coefficients pointer is not preset after each iteration. 1 = The coefficients pointer is preset after each iteration to the CBASE pointer. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. 16-52 MPC823e REFERENCE MANUAL MOTOROLA...
Page 507 16.3.4.4.4 Application Example. The FIR5 function is used in the fractionally spaced equalizer. The following example demonstrates how the function descriptor structure can be used to implement a fractionally spaced equalizer. 00101 OFFSET + 0 I=1 (ONE ITERATION) OFFSET + 2 MOTOROLA MPC823e REFERENCE MANUAL 16-53...
Page 508 16-bit half-word. The new sample is stored in the address that follows the previous sample. The output buffer is a cyclic buffer that contains N+1 bytes and the new output is stored in the address that follows the previous output. 16-54 MPC823e REFERENCE MANUAL MOTOROLA...
Page 509 OFFSET + C RESERVED OFFSET + E The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. MOTOROLA MPC823e REFERENCE MANUAL 16-55...
Page 510 0 = The coefficients pointer is not preset after each iteration. 1 = The coefficients pointer is preset after each iteration to the CBASE pointer. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. 16-56 MPC823e REFERENCE MANUAL MOTOROLA...
Page 511 M+1 bytes. Each sample is a 16-bit half-word and the new sample is stored in the address that follows the previous sample. The output buffer is a cyclic buffer that contains N+1 bytes and the new output is stored in the address that follows the previous one. MOTOROLA MPC823e REFERENCE MANUAL 16-57...
Page 512 The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executiing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1, 4–5, and 8–10—Reserved These bits are reserved and must be set to 0. 16-58 MPC823e REFERENCE MANUAL MOTOROLA...
Page 513 Output Buffer Size-1. The minimum output buffer size is 4 (2 outputs). Half-word 7 Reserved 16.3.4.6.4 Application Example. Among other things, the IIR is used in timing recovery and an interpolating filter. INDEX 00111 OFFSET + 0 I=1 (ONE ITERATION) OFFSET + 2 MOTOROLA MPC823e REFERENCE MANUAL 16-59...
Page 514 K + 1 bytes M + 1 bytes N + 1 bytes N + 1 bytes Figure 16-25. MOD Table and Sample Data Buffers 16-60 MPC823e REFERENCE MANUAL MOTOROLA...
Page 515 1 = The real and imaginary parts of the result is written to the output buffer. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this table. MOTOROLA MPC823e REFERENCE MANUAL 16-61...
Page 516 ωnT, sin ωnT, AGC {REAL} REAL Y n ( ) × n ( ) × ωnT 1 AGC IMAG Y n ( ) × n ( ) × ωnT – ( 1 AGC Figure 16-26. DEMOD Implementation Example 16-62 MPC823e REFERENCE MANUAL MOTOROLA...
Page 517 16.3.4.8.2 DEMOD Function Descriptor. The DEMOD function descriptor bit table is described below. OPCODE OFFSET + 0 OFFSET + 2 OFFSET + 4 DPTR OFFSET + 6 OFFSET + 8 XYPTR OFFSET + A OFFSET + C RESERVED OFFSET + E MOTOROLA MPC823e REFERENCE MANUAL 16-63...
Page 518 Half-word 5 XYPTR Pointer to a structure composed of the input sample data pointer and the output buffer pointer Half-word 6 Output Buffer Size-1. The minimum output buffer size is 8 (2 outputs). Half-word 7 Reserved 16-64 MPC823e REFERENCE MANUAL MOTOROLA...
Page 519 COEFFICIENTS INPUT SAMPLES imag{C(0)} real{C(0)} imag{C(1)} real{C(1)} imag{X(n-k+1)} real{X(n-k+1)} imag{C(k-1)} real{C(k-1)} imag{X(n-2)} real{X(n-2)} imag{X(n-1)} real{X(n-1)} imag{X(n)} real{X(n)} 2K bytes M + 1 bytes Figure 16-29. LMS1 Coefficients and Sample Data Buffers MOTOROLA MPC823e REFERENCE MANUAL 16-65...
Page 520 10 = The X (input) pointer is incremented by two samples. 11 = The X (input) pointer is incremented by three samples. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. 16-66 MPC823e REFERENCE MANUAL MOTOROLA...
Page 521 The coefficients and input samples are complex numbers, but the scalar is a real or complex number. C n 1 C n i E X n i – × Figure 16-30. LMS2 Implementation Example MOTOROLA MPC823e REFERENCE MANUAL 16-67...
Page 522 16.3.4.10.2 LMS2 Function Descriptor. The LMS2 function descriptor bit table is described below. INDEX OPCODE OFFSET + 0 RESERVED OFFSET + 2 OFFSET + 4 CBASE OFFSET + 6 OFFSET + 8 XPTR OFFSET + A EPTR OFFSET + C RESERVED OFFSET + E 16-68 MPC823e REFERENCE MANUAL MOTOROLA...
Page 523 10 = The X (input) pointer is incremented by two samples. 11 = The X (input) pointer is incremented by three samples. OPCODE—Function Operation Code This field specifies the function to be executed. Table 16-6 contains the value for this field. MOTOROLA MPC823e REFERENCE MANUAL 16-69...
Page 524 β = 1 − α and (0 ≤ α ≤1) generates a linear interpolation between the two input vectors. Y n ( ) αX 1 n ( ) βX 2 n ( ) Figure 16-32. WADD Implementation Example 16-70 MPC823e REFERENCE MANUAL MOTOROLA...
Page 525 16.3.4.11.2 WADD Function Descriptor. The WADD function descriptor bit table is described below. OPCODE OFFSET + 0 OFFSET + 2 OFFSET + 4 OFFSET + 6 OFFSET + 8 XYPTR OFFSET + A OFFSET + C RESERVED OFFSET + E MOTOROLA MPC823e REFERENCE MANUAL 16-71...
Page 526 Samples Buffer Size-1 Half-word 5 XYPTR Pointer to a structure composed of X input sample data pointer, output buffer pointer, and the X input sample data pointer. Half-word 6 EPTR Output Buffer Size-1 Half-word 7 Reserved 16-72 MPC823e REFERENCE MANUAL MOTOROLA...
Page 527 42 + 7 ∗ (K+1) LMS2 46 + 7 ∗ Ι WADD NOTES: Add 1 clock for wrap, 5 clocks for stop, and 4 clocks for interrupt. i = number of iterations. k+1 = number of taps. MOTOROLA MPC823e REFERENCE MANUAL 16-73...
Page 528 • Output compare with programmable mode for the output pin • Four timers can be internally or externally cascaded to form two 32-bit timers. Timer 1 exclusive-Or’ed with SPKR input from PCMCIA to generate SPKROUT • Free run and restart modes 16-74 MPC823e REFERENCE MANUAL MOTOROLA...
Page 529 TGATE1 pin and disables the count on the rising edge of the TGATE1 pin. This mode allows the timer to count conditionally, depending on the state of the TGATE1 pin. MOTOROLA MPC823e REFERENCE MANUAL 16-75...
Page 530 The capture is controlled by the TIN2 pin and the interrupts are generated by the timer event 2 register. When operating in cascaded mode, the cascaded timer reference register, timer capture register, and timer counter must always be referenced with 32-bit bus cycles. 16-76 MPC823e REFERENCE MANUAL MOTOROLA...
Page 531 1 = Enable the corresponding timer if the STPx bit is cleared. Bit 4—Reserved This bit is reserved and must be set to 0. CAS2—Cascade Timers 0 = Normal operation. 1 = Timers 1 and 2 are cascaded to form a 32-bit timer. MOTOROLA MPC823e REFERENCE MANUAL 16-77...
Page 532 1 = Toggle the TOUTx pin. Changes to TOUTx occur on the falling edge of the system clock. ORI—Output Reference Interrupt Enable 0 = Disable interrupt for reference that is reached. This does not affect an interrupt on the capture function. 1 = Enable interrupt when the reference value is reached. 16-78 MPC823e REFERENCE MANUAL MOTOROLA...
Page 533 TRR1–TRR4 FIELD REFERENCE RESET ADDR (IMMR & 0xFFFF0000) + 0x994 (TRR1), 0x996 (TRR2), 0x9A4 (TRR3), 0x9A6 (TRR4) REFERENCE—Reference to TCNx This reference value is reached when the TCNx register increments to equal the TRRx register. MOTOROLA MPC823e REFERENCE MANUAL 16-79...
Page 534 Note: The TCNx register may not be updated correctly if a write is made to it while the timer is not running. You must always use the TRRx register to define the preferred counter value. 16-80 MPC823e REFERENCE MANUAL MOTOROLA...
Page 535 3. Write 0x0000 to the TCN2. This initializes the timer 2 count to zero (default state of this register). 4. Write 0x00FA to the TRR2. This initializes the timer 2 reference value to 250 (decimal). MOTOROLA MPC823e REFERENCE MANUAL 16-81...
Page 536 On a path 2 access, only the U-Bus needs to be acquired and the access is not seen on the external system bus, unless the MPC823e is configured into the “show cycles” mode of the system interface unit. Thus, transfers on the U-Bus occur at the same time that other operations occur on the external system bus.
Page 537 Each SDMA channel can be programmed to output one of eight function codes that identify the channel currently accessing memory. The SDMA channel can be assigned a big-endian (Motorola) or little-endian format for accessing buffer data. These features are programmed in the receive and transmit function code registers that are associated with the serial communication controllers, serial management controllers, serial peripheral interface, and C controller.
Page 538 SDMA bus cycles. The entire operand (4-word burst, 32 bits on reads, and 8, 16, or 32 bits on writes) will be transferred in back-to-back bus cycles before the SDMA relinquishes the bus. The SDMA can steal cycles with no arbitration overhead when the MPC823e is bus master. OTHER CYCLE SDMA CYCLE...
Page 539 The control provided by this register has interactions with the DMA controllers in the LCD and video controller modules of the MPC823e. Refer to Section 18.3.6 DMA Control and Section 18.3.1 FIFO Control for more information regarding those modules.
Page 540 00 = The SDMA uses U-Bus arbitration priority 6 (highest). 01 = The SDMA uses U-Bus arbitration priority 5. 10 = The SDMA uses U-Bus arbitration priority 2. 11 = The SDMA uses U-Bus arbitration priority 1 (lowest). 16-86 MPC823e REFERENCE MANUAL MOTOROLA...
Page 541 DSP1—DSP Chain 1 Receiver Interrupt (DSP function) This bit is set when the chain 1 function finishes executing. However, the I bit must be set in the function descriptor, as described in Section 16.3.3.3 DSP Event Register. MOTOROLA MPC823e REFERENCE MANUAL 16-87...
Page 542 1 = Enable the DSP chain 2 transmitter interrupt. DSP1—DSP Chain 1 Receiver Interrupt Mask (DSP function) 0 = Disable the DSP chain 1 receiver interrupt, as described in Section 16.3.3.3 DSP Event Register. 1 = Enable the DSP chain 1 receiver interrupt. 16-88 MPC823e REFERENCE MANUAL MOTOROLA...
Page 543 The chip-select and wait-state generation logic on the MPC823e can be used with IDMA. IDMA supports three buffer handling modes—single buffer, autobuffer, and buffer chaining.
Page 544 When the peripheral asks for IDMA service, it asserts DREQx and the MPC823e begins the IDMA process. While the service is in progress, SDACKx is asserted during accesses to the device. DREQx can be configured to be either edge- or level-sensitive by programming the DRxM field in the RCCR.
Page 545 The data associated with each IDMA channel for autobuffer and buffer chaining modes is stored in buffers and each buffer is referenced by a buffer descriptor that uses a ring structure located in the dual-port RAM. MOTOROLA MPC823e REFERENCE MANUAL 16-91...
Page 546 Communication Processor Module 16.6.3.2 IDMA PARAMETER RAM MEMORY MAP. The MPC823e uses the IDMA parameters listed in the table below to configure the IDMA channel for autobuffer or buffer chaining mode. Table 16-21. IDMA Parameter RAM Memory Map ADDRESS NAME...
Page 547 IBASE register. • WRITE_SP—This parameter must not be modified. • S_BYTE_C—This parameter must not be modified. • D_BYTE_C—This parameter must not be modified. MOTOROLA MPC823e REFERENCE MANUAL 16-93...
Page 548 This bit indicates when the IDMA channel terminates a transfer. It is set after servicing a buffer descriptor that has the L status bit set. OB—Out of Buffers This bit indicates that the IDMA channel has no valid buffer descriptors. 16-94 MPC823e REFERENCEMANUAL MOTOROLA...
Page 549 This bit indicates when the IDMA channel terminates a transfer. It is set after servicing a buffer descriptor that has the L status bit set. OB—Out of Buffers This bit indicates that the IDMA channel has no valid buffer descriptors. MOTOROLA MPC823e REFERENCE MANUAL 16-95...
Page 550 Note: The only difference between autobuffer mode and buffer-chaining mode is that the V bit is not cleared by the RISC microcontroller in autobuffer mode. Autobuffer mode is enabled by the CM bit. 16-96 MPC823e REFERENCEMANUAL MOTOROLA...
Page 551 Either a single buffer descriptor or multiple buffer descriptors can be used in this mode to create an infinite loop of repetitive data moves. Note: The I bit can be used to generate an interrupt in this mode. MOTOROLA MPC823e REFERENCE MANUAL 16-97...
Page 552 00 = The DEC/Intel convention is used for byte ordering (swapped operation). It is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode can only be used with 32-bit port size memory.
Page 553 00 = The DEC/Intel convention is used for byte ordering (swapped operation). It is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode can only be used with 32-bit port size memory.
Page 554 IDMA transfers. The DONE bit is set in the IDSRx and the current buffer descriptor is closed. If the peripheral device is the source, the IDMA internal buffer is transferred to memory before termination. At the next request, the following buffer descriptor in the chain is processed. 16-100 MPC823e REFERENCEMANUAL MOTOROLA...
Page 555 SDACKx signal. The device is either the source or destination of the transfers, as determined by the TYPE field of the DCMR. Thus, SDACKx is the acknowledgment of the original cycle steal request given on the DREQx pin. MOTOROLA MPC823e REFERENCE MANUAL 16-101...
Page 556 D_BYTE_C is decremented by the number of bytes transferred. If it is equal to zero and the transfer is completed with no errors, the DONE bit in the IDSRx is set. Refer to Section 16.6.3.2 IDMA Parameter RAM Memory Map for more information. 16-102 MPC823e REFERENCEMANUAL MOTOROLA...
Page 557 For more details about IDMA handshake signals, refer to Section 16.6.2 IDMA Interface Signals. For specific timing parameters, visit our website. CLKOUT ADDRESS RD / DATA SDACKx DREQx Figure 16-39. Single-Address, Peripheral Write, Asynchronous TA MOTOROLA MPC823e REFERENCE MANUAL 16-103...
Page 558 SIZE field in the DCMR. The data bus is driven to three-state for this write cycle. For more details about IDMA handshake signals, refer to Section 16.6.2 IDMA Interface Signals. For specific timing parameters, visit our website. 16-104 MPC823e REFERENCEMANUAL MOTOROLA...
Page 559 (odd or even) and a frame is composed of several fields. The refresh (of the display) or readout (of the CCD) is done by field sequence—field1, then field2, etc. Note: The ARM IDMA command only works with IDMA modes that use buffer descriptors. MOTOROLA MPC823e REFERENCE MANUAL 16-105...
Page 560 * Modified by the IDMA controller during operation and must be reinitialized before starting a new IDMA transaction. DMA base = (IMMR & 0xFFFF0000) + 0x3CC0 (IDMA1). All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as a memory-based register. 16-106 MPC823e REFERENCEMANUAL MOTOROLA...
Page 561 (IMMR & 0xFFFF0000) + 0x3CCA MB1—Must Be 1 For DMA operation, this bit must be set to 1. Bits 1–2, 9 11, 16 31—Reserved — — These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-107...
Page 562 00 = DEC/Intel convention is used for byte ordering (swapped operation). It is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed as compared to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 563 These bits are reserved and must be set to 0. DONE—IDMA Transfer Done This bit indicates that the IDMA channel terminated a transfer. It will be set after the byte count in the BCR of the single-buffer mode parameter RAM has reached zero. MOTOROLA MPC823e REFERENCE MANUAL 16-109...
Page 564 DREQ1 pin before the last beat of the transfer. Otherwise, IDMA will assume that another DMA request is pending and will start another burst cycle right after the completion of the current transfer. 16-110 MPC823e REFERENCEMANUAL MOTOROLA...
Page 565 0x22021FF) and 256 bytes at the end of the first 4K (on the ADS address 0x2202F00 to address 0x2202FFF).Use the following MPC8bug debugger commands to load the package: rms cpm rccr 0 load interlaced_dma.srx rms cpm rccr 9 MOTOROLA MPC823e REFERENCE MANUAL 16-111...
Page 566 When a synchronous bus structure like those supported by the MPC823e is used, you can make provisions that allow a bus master to detect and respond to errors during a bus cycle. IDMA recognizes the same bus exceptions that the core recognizes at reset or when a transfer error occurs.
Page 567 TO SMC2 TO SCC2 TO SCC3 TO SMC1 USB CLOCKS TIME-SLOT ASSIGNER TDMA/SMC2/TDMB TDMA AND TDMB SMC1 SCC2 SCC3 PINS PINS PINS STROBE PINS PINS PINS NONMULTIPLEXED SERIAL INTERFACE (NMSI) Figure 16-43. Serial Interface Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 16-113...
Page 568 TDM buses, including the T1 and CEPT highways, pulse code modulation (PCM) highway, and ISDN buses in both basic and primary rates. The two popular ISDN basic rate buses—interchip digital link and general circuit interface (also known as IOM-2) are supported. 16-114 MPC823e REFERENCE MANUAL MOTOROLA...
Page 569 RAMs that are directly accessible by the host CPU in the internal register section of the MPC823e and are not associated with the dual-port RAM. One serial interface RAM is always used to program the transmit routing and the other is used to program the receive routing.
Page 570 Most Complex TDM Example—Totally Independent RX and TX MPC82x TDM TX SYNC TDM TX CLOCK SCC2 SMC1 SCC2 TDM TX TDM RX SYNC TDM RX CLOCK TDM RX SMC1 SCC2 Figure 16-44. Various Configurations With the TDM Channel 16-116 MPC823e REFERENCE MANUAL MOTOROLA...
Page 571 TDM channels: • One multiplexed channel with static frames • One multiplexed channel with dynamic frames • Two multiplexed channels with static frames • Two multiplexed channels with dynamic frames MOTOROLA MPC823e REFERENCE MANUAL 16-117...
Page 572 RDM = 00 ONE CHANNEL WITH INDEPENDENT RX AND TX ROUTE FRAMING SIGNAL SERIAL INTERFACE RAM ENTRY L1RCLK BITS WIDE) L1RSYNCA 64 ENTRIES ROUTE L1TCLKA L1TSYNCA 64 ENTRIES ROUTE Figure 16-46. Configuring the TDM with Static Frames 16-118 MPC823e REFERENCE MANUAL MOTOROLA...
Page 573 ONE CHANNEL WITH SHADOW RAM FOR DYNAMIC ROUTE CHANGE FRAMING SIGNALS SERIAL INTERFACE RAM ENTRY BITS WIDE) L1RCLKx L1RSYNCx 32 ENTRIES ROUTE L1TCLK x L1TSYNC x 32 ENTRIES ROUTE Figure 16-47. Configuring the TDM with Dynamic Frames MOTOROLA MPC823e REFERENCE MANUAL 16-119...
Page 574 FRAMING SIGNALS FRAMING SIGNALS (32 BITS WIDE) L1RCLKA L1RCLKB L1RSYNCA L1RSYNCB 32 ENTRIES 32 ENTRIES ROUTE ROUTE L1TCLKA L1TCLKB L1TSYNCA L1TSYNCB 32 ENTRIES 32 ENTRIES ROUTE ROUTE Figure 16-48. Configuring two TDMs with Static Frames 16-120 MPC823e REFERENCE MANUAL MOTOROLA...
Page 575 (32 BITS WIDE) L1RCLKA L1RCLK b L1RSYNCA L1RSYNC b 16 ENTRIES 16 ENTRIES ROUTE ROUTE L1TCLKA L1TCLK b L1TSYNCA 16 ENTRIES L1TSYNC b 16 ENTRIES ROUTE ROUTE Figure 16-49. Configuring Two TDMs with Dynamic Frames MOTOROLA MPC823e REFERENCE MANUAL 16-121...
Page 576 TDM receive data and transmit on the same TDM transmit signal. TDM RECEIVE DATA TDM TRANSMIT DATA STATION A STATION B Figure 16-50. Using the SWTR Bit 16-122 MPC823e REFERENCE MANUAL MOTOROLA...
Page 577 Note: Each strobe is changed with the corresponding RAM clock and is only output if the corresponding parallel I/O is configured as a dedicated pin. Bit 6—Reserved This bit is reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-123...
Page 578 Communication Processor Module CSEL—Channel Select 000 = The bit/byte group is not supported by the MPC823e. The transmit data pin is three-stated and the receive data pin is ignored. 001 = Reserved. 010 = The bit/byte group is routed to SCC2.
Page 579 If a TDM with dynamic changes is programmed, the initial current-route RAM addresses in the serial interface RAM are as follows: • 0–31 RXA Route • 64–95 TXA Route The shadow RAMs are at addresses: • 32–63 RXA Route • 96–127 TXA Route MOTOROLA MPC823e REFERENCE MANUAL 16-125...
Page 580 Interface RAM Pointer Register . You can also externally connect one of the eight strobes to an interrupt pin to generate an interrupt on a particular serial interface RAM entry starting or ending execution by the time-slot assigner. 16-126 MPC823e REFERENCE MANUAL MOTOROLA...
Page 581 THE SHADOW AND THE CURRENT-ROUTE RAMS L1RCLKA FRAMING SIGNALS: AND RESETS THE CSR L1RSYNCA CSRRA=0 RAM ADDRESS: CSRTA=0 16 TXA 16 TXA SHADOW ROUTE L1TCLKA FRAMING SIGNALS: L1TSYNCA Figure 16-51. Serial Interface RAM Dynamic Changes MOTOROLA MPC823e REFERENCE MANUAL 16-127...
Page 582 16 for transmit routing for each channel. There are an additional 16 shadow entries for the receive routing and 16 more for transmit routing that can be used to dynamically change the channel routing. 16-128 MPC823e REFERENCE MANUAL MOTOROLA...
Page 583 0 = NMSI mode. The clock source is determined by the SMC1CS field and the data comes from a dedicated pin SMTXD1 and SMRXD1 in NMSI mode. 1 = SMC1 is connected to the multiplexed serial interface (TDM channel). MOTOROLA MPC823e REFERENCE MANUAL 16-129...
Page 584 Use for GCI. 01 = 1-bit delay. Use for IDL. 10 = 2-bit delay. 11 = 3-bit delay. See the examples in Figure 16-52 and Figure 16-53 to find out how to use these bits. 16-130 MPC823e REFERENCE MANUAL MOTOROLA...
Page 585 The grant is a sample of the L1GRA pin while L1TSYNCx is asserted. This grant mechanism implies the IDL access controls for transmission on the D channel. Refer to Section 16.7.6.2 Programming the IDL Interface for more information. MOTOROLA MPC823e REFERENCE MANUAL 16-131...
Page 586 BIT 2 BIT 3 BIT 4 BIT 0 BIT 1 BIT 2 NO DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME Figure 16-53. Example of No Delay from Sync to Data (RFSDx = 00) 16-132 MPC823e REFERENCE MANUAL MOTOROLA...
Page 587 (FEx=0) L1xSYNC (FEx=1) L1xSYNC L1TXDx (BIT 0) L1STx (ON BIT 0) L1STx DRIVEN FROM CLOCK HIGH FOR BOTH FEx SETTINGS RX SAMPLED HERE Figure 16-55. Example of Clock Edge (CE) Effect When DSCx = 1 MOTOROLA MPC823e REFERENCE MANUAL 16-133...
Page 588 L1xSYNC L1TXDx (BIT 0) L1STx AND DATA BIT 0 IS DRIVEN FROM CLOCK LOW L1STx (ON BIT 0) Figure 16-56. Example of Frame Transmission Reception When RFSDx or TFSDx = 0 and CD = 1 16-134 MPC823e REFERENCE MANUAL MOTOROLA...
Page 589 L1xSYNC (FEx=0) L1TXDx (BIT 0) BOTH THE DATA AND L1STx FROM THE CLOCK WHEN ASSERTED DURING CLOCK LOW L1STx (ON BIT 0) Figure 16-57. Example of CEx = 0 and FEx Interaction, XFSD = 0 MOTOROLA MPC823e REFERENCE MANUAL 16-135...
Page 590 I/O port pins or dedicated SCC3 pins in the parallel I/O port registers. See Section 16.14 The Parallel I/O Ports for more information. 1 = SCC3 is connected to the multiplexed serial interface. The NMSI3 receive pins are available for other purposes. 16-136 MPC823e REFERENCE MANUAL MOTOROLA...
Page 591 I/O port pins or dedicated SCC2 pins in the parallel I/O port registers. See Section 16.14 The Parallel I/O Ports for more information. 1 = SCC2 is connected to the multiplexed serial interface. The NMSI2 receive pins are available for other purposes. MOTOROLA MPC823e REFERENCE MANUAL 16-137...
Page 592 100 = USB clock is CLK1. 101 = USB clock is CLK2. 110 = USB clock is CLK3. 111 = USB clock is CLK4. Bits 29–31—Reserved These bits are reserved and must be set to 0. 16-138 MPC823e REFERENCE MANUAL MOTOROLA...
Page 593 RAMs and take the new transmitter routing from the receiver shadow RAM. This bit is cleared as soon as the switch has completed. Bits 2–7—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-139...
Page 594 This bit is valid in the RAM division mode (RDM field in the SIGMR = 11). 0 = The current-route transmitter RAM is in address 192-223. 1 = The current-route transmitter RAM is in address 224-255. Bits 4–7—Reserved These bits are reserved and must be set to 0. 16-140 MPC823e REFERENCE MANUAL MOTOROLA...
Page 595 The pointers provided by this register indicate the serial interface RAM entry word offset that is currently in progress. SIRP FIELD RESERVED TBPTR RESERVED TAPTR RESET ADDR (IMMR & 0xFFFF0000) + 0xAF0 FIELD RESERVED RBPTR RESERVED RAPTR RESET ADDR (IMMR & 0xFFFF0000) + 0xAF2 MOTOROLA MPC823e REFERENCE MANUAL 16-141...
Page 596 • TxPTR contains the address of the currently active TX RAM entry. When the serial interface services entries 1–32, TAPTR is incremented and TBPTR is continuously cleared. When the serial interface services entries 33–64, TAPTR is continuously cleared and TBPTR is incremented. 16-142 MPC823e REFERENCE MANUAL MOTOROLA...
Page 597 0–15, the current-route RAM is SI RAM address block 128–159 and the CROTA bit is set to 0 in the SISTR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address block 160–191 and CROTA is set to 1 in the SISTR. MOTOROLA MPC823e REFERENCE MANUAL 16-143...
Page 598 MPC823e. The basic and primary rate of the IDL bus is supported by the MPC823e. In the basic rate of IDL, data on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing 160kbps full-duplex bandwidth. The MPC823e is an IDL slave device that is clocked by the IDL bus master (physical layer device) and has separate receive and transmit sections.
Page 599 • L1RSYNCx—IDL sync pin. Input to the MPC823e. This signal indicates that the clock periods following the pulse designate the IDL frame. • L1RXDx—IDL receive data pin. Input to the MPC823e. Valid only for the bits that are supported by the IDL and ignored for other signals that may be present.
Page 600 Communication Processor Module There are two definitions of the IDL bus frame structure—8 and 10 bits. The only difference between them is the channel order within the frame. Figure 16-59. IDL Terminal Adaptor 16-146 MPC823e REFERENCE MANUAL MOTOROLA...
Page 601 IDL control channel would be out-of-band. They were defined as a subset of the Motorola SPI format called serial control port (SCP). If you prefer to implement the A and M bit functions as originally defined, you can program the time-slot assigner to access these bits and route them transparently to a serial communication controller or serial management controller.
Page 602 Communication Processor Module The MPC823e supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame can be routed to every serial communication controller and serial management controller or they can assert a strobe output that supports an external device.
Page 603 5 is set to 0. L1RSYNCA is an input, but it does not need to be configured with a PCDIR bit. 9. TheSIGMR equals 0x04. Enable TDMA (one static TDM). 10. The SICMR is not used. MOTOROLA MPC823e REFERENCE MANUAL 16-149...
Page 604 • L1RSYNC x —Used as a GCI sync signal. Input to the MPC823e. This signal indicates that the clock periods following the pulse designate the GCI frame. • L1RCLK x —Used as a GCI clock. Input to the MPC823e. The L1RCLK x signal is twice the data clock.
Page 605 The MPC823e supports contention detection on the D channel of the SCIT bus. When the MPC823e has data to transmit on the D channel, it checks a SCIT bus bit that is marked with a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the physical layer bus for activity on the D channel and indicates on this bit that the channel is free.
Page 606 D channel serial communication controller as the grant. The bit is generally bit 4 of the C/I in channel 2 of GCI, but any other bit can be selected using the serial interface RAM. 16-152 MPC823e REFERENCE MANUAL MOTOROLA...
Page 607 6. In the PADIR, bits 9 and 8 are set to 1 and in the PADIR, bit 7 is set to 0. Configure L1TXDA, L1RXDA, and L1RCLKA. 7. In the PCPAR, bit 4 is set to 1. Configure L1RSYNCA. 8. The SIGMR equals 0x04.Enable TDMA (one static TDM). 9. The SICMR is not used. MOTOROLA MPC823e REFERENCE MANUAL 16-153...
Page 608 I/O lines. Therefore, if some combination of the TDM and NMSI channels is used, you must consult the MPC823e pinout in Section 2 External Signals to decide if (and where) you plan to connect a serial communication controller or serial management controller.
Page 609 Figure 16-62. Bank of Clocks The modem control pins for the USB in NMSI mode are as follows: • USBRXD • USBRXP • USBTXP • USBCLK ← BRG1–BRG4, CLK1–CLK4 • USBRXN • USBTXN • USBOE MOTOROLA MPC823e REFERENCE MANUAL 16-155...
Page 610 • SMTXD2 • SMRXD2 • SMCLK2 ← BRG1–BRG4, CLK1–4 • SMSYN2 (used only in the totally transparent protocol) Unused USB, SCC or SMC signals can be used for other functions or configured for parallel I/O. 16-156 MPC823e REFERENCE MANUAL MOTOROLA...
Page 611 12 BIT BRGO AND/OR CLK4 PIN DIVIDE BY COUNTER CLOCK BANK OF 1–4,096 1 OR 16 BRGCLK CLOCKS ATB BIT AUTOBAUD RX SOURCE CONTROL TX SOURCE BAUD RATE GENERATOR Figure 16-63. Baud Rate Generator Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 16-157...
Page 612 The clock input to the prescaler can be selected by the EXTC field in the baud rate generator configuration registers to originate in one of three sources—BRGCLK, CLK2 or CLK4. The BRGCLK is generated in the MPC823e clock synthesizer specifically for the four baud rate generators, serial peripheral interface, and I C internal baud rate generator.
Page 613 The MPC823e baud rate generators have a built-in autobaud control function that automatically measures the length of a start bit and modifies the baud rate accordingly. If the ATB bit in...
Page 614 This bit is used to dynamically stop the baud rate generator from counting, which may be useful for low-power modes. 0 = Stop all clocks to the baud rate generator. 1 = Enable clocks to the baud rate generator. 16-160 MPC823e REFERENCE MANUAL MOTOROLA...
Page 615 The terminal count signals counter expiration and toggles the clock. DIV16—BRG Clock Prescaler Divide by 16 0 = Divide by 1 for the clock divider input. 1 = Divide-by-16 prescaler enabled for the clock divider output. MOTOROLA MPC823e REFERENCE MANUAL 16-161...
Page 616: Uart Baud Rate Examples
UART to 16× oversampling when using a serial communication controller in UART mode. On the MPC823e, 8× and 32× options are also available. Assuming 16× oversampling is chosen in the UART, a data rate of 25MHz ÷ 16 = 1.5625Mb/sec is the maximum possible UART speed.
Page 617 = 389. 16.9 THE SERIAL COMMUNICATION CONTROLLERS The MPC823e has two serial communication controllers (SCC2 and SCC3) that can be configured independently to implement different protocols. They can be used to implement bridging functions, routers, gateways, and interface with a wide variety of standard WANs, LANs, and proprietary networks.
Page 618 For information about the serial communication controller command set, see Table 16-2. A serial communication controller can be connected to its own set of pins on the MPC823e. This configuration is called the nonmultiplexed serial interface (NMSI) and is described in Section 16.7 The Serial Interface with Time-Slot Assigner .
Page 619 • Low FIFO latency option for transmit and receive in character-oriented and totally transparent protocols • Frame preamble options • Full-duplex operation • Fully transparent option for receiver/transmitter while another protocol executes on the transmitter/receiver • Echo and local loopback modes for testing MOTOROLA MPC823e REFERENCE MANUAL 16-165...
Page 620 Lastly, this option must be chosen if external clocks are used and if it is more important to minimize power consumption than to watch for glitches. 1 = Glitch detection is performed with a maskable interrupt generated in the SCCE register. 16-166 MPC823e REFERENCE MANUAL MOTOROLA...
Page 621 Ethernet on the transmitter or while transparent operation is on the receiver. In other words, if the MODE field is set for Ethernet, then TTX must equal TRX or erratic operation will occur. MOTOROLA MPC823e REFERENCE MANUAL 16-167...
Page 622 As soon as CDx is low, data is received. This mode is especially useful when connecting an MPC823e in transparent mode because it allows the RTSx signal of one MPC823e to be directly connected to the CDx signal of another MPC823e.
Page 623 As soon as CTSx is low, data immediately begins transmission. This mode is especially useful when connecting an MPC823e in transparent mode since it allows the RTSx signal of one MPC823e to be directly connected to the CTSx signal of another MPC823e.
Page 624 GSMR_L FIELD EDGE TSNC RINV TINV TEND TDCR RESET ADDR (IMMR & 0xFFF0000) + 0xA20 FIELD RDCR RENC TENC DIAG MODE RESET ADDR (IMMR & 0xFFF0000) + 0xA22 16-170 MPC823e REFERENCE MANUAL MOTOROLA...
Page 625 01 = 14- or 6.5-bit times as determined by the RDCR field. 10 = 4- or 1.5-bit times as determined by the RDCR field (normally for AppleTalk). 11 = 3- or 1-bit times as determined by the RDCR field. MOTOROLA MPC823e REFERENCE MANUAL 16-171...
Page 626 00 = All zeros. 01 = Repetitive 10s. Select this setting for Ethernet operation. 10 = Repetitive 01s. 11 = All ones. Select this setting for LocalTalk operation. 16-172 MPC823e REFERENCE MANUAL MOTOROLA...
Page 627 00 = 1x clock mode. Only NRZ or NRZI decodings are allowed. 01 = 8x clock mode. 10 = 16x clock mode. Normally chosen for UART and AppleTalk. 11 = 32x clock mode. MOTOROLA MPC823e REFERENCE MANUAL 16-173...
Page 628 I/O register. In the SDMx field of the SIMODE register, the L1TXDx and L1RQx signals can be programmed to be either asserted normally or to remain inactive. See Section 16.7.5.2 Serial Interface Mode Register for more information. 16-174 MPC823e REFERENCE MANUAL MOTOROLA...
Page 629 Note: The serial communication controller that controls reception provides other tools besides the ENR bit. Some of these tools include the ENTER HUNT MODE command, CLOSE RX BD command, and the E bit of the receive buffer descriptor. MOTOROLA MPC823e REFERENCE MANUAL 16-175...
Page 630 MODE field of the GSMR_L. Each serial communication controller has an additional 16-bit, memory-mapped, read/write protocol-specific mode register (PSMR) that configures it for a particular mode. Since every SCCx protocol has specific requirements, the PSMR bits are different for each protocol. 16-176 MPC823e REFERENCE MANUAL MOTOROLA...
Page 631 Therefore, it is recommended that you only use the transmit-on-demand feature when a high-priority TX buffer descriptor has been prepared and if a sufficient amount of time has passed since a serial communication controller was transmitted. MOTOROLA MPC823e REFERENCE MANUAL 16-177...
Page 632 The MPC823e internal memory has enough space for 224 buffer descriptors (BDs) to be shared between the universal serial bus, serial communication controllers, serial managment controllers, serial peripheral interface, and C controller.
Page 633 TBASE (RBASE) points to in the table. The number of TX buffer descriptors in the ring are programmable and determined only by the W bit and overall space constraints of the dual-port RAM. MOTOROLA MPC823e REFERENCE MANUAL 16-179...
Page 634 TX DATA BUFFER TABLE DATA POINTER RX BUFFER DESCRIPTORS SCCx RX BD TABLE FRAME STATUS DATA LENGTH RX DATA BUFFER DATA POINTER SCCx RX BD TABLE POINTER SCCx TX BD TABLE POINTER Figure 16-65. SCCx Memory Structure 16-180 MPC823e REFERENCE MANUAL MOTOROLA...
Page 635 E bit to 0 and never uses a buffer descriptor twice until it has been processed by the core. The one exception to this rule is that the MPC823e supports an option for repeated reception called continuous mode, whereby the E bit stays set to 1. This is available in some protocols.
Page 636 RESTART TRANSMIT command is executed. • The parameter RAM values related to the SCCx receiver can only be written when the receiver is disabled. Refer to Section 16.9.14 Disabling the SCCs On-the-Fly for more information. 16-182 MPC823e REFERENCE MANUAL MOTOROLA...
Page 637 However, you must initialize these entries before enabling the corresponding channel. Note: RBASE and TBASE must contain a value that is divisible by eight. MOTOROLA MPC823e REFERENCE MANUAL 16-183...
Page 638 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 639 MPC823e writes to a receive buffer on a serial communication controller before it moves on to the next buffer. The MPC823e can write fewer bytes to the buffer than MRBLR if a condition, such as an error or end-of-frame occurs, but it never writes more bytes than the MRBLR value.
Page 640 SDMA channels. RSTATE, TSTATE, RTMP, TTMP, and reserved areas must only be used by the RISC microcontroller. Note: To extract data from a partially full receive buffer, issue the CLOSE RX BD command. 16-186 MPC823e REFERENCE MANUAL MOTOROLA...
Page 641 RXDx signal. It does not show the real-time status of the CTSx and CDx pins. Their real- time status is available in the port C parallel I/O. Since every SCCx protocol has specific requirements, the SCCS bits are different for each protocol. MOTOROLA MPC823e REFERENCE MANUAL 16-187...
Page 642 3. Extract data from the RX buffer descriptor if the RX, RXB, or RXF bit is set in the SCCE register. If the receive speed is fast or the interrupt delay is long, more than one 16-188 MPC823e REFERENCE MANUAL MOTOROLA...
Page 643 FIRST BIT OF FRAME DATA RTSx LAST BIT OF FRAME DATA (OUTPUT) CTSx (INPUT) NOTE: A frame includes opening and closing flags and syncs, if present in the protocol. Figure 16-66. RTSx Output Delays Asserted for Synchronous Protocols MOTOROLA MPC823e REFERENCE MANUAL 16-189...
Page 644 LAST BIT OF FRAME DATA RTSx FIRST BIT OF FRAME DATA (OUTPUT) CTSx (INPUT) NOTE: CTSS is set to 1 in the GSMR. CTSP is a "don't care". Figure 16-67. CTSx Output Delays Asserted for Synchronous Protocols 16-190 MPC823e REFERENCE MANUAL MOTOROLA...
Page 645 NOTE: CTSS is set to 1 in the GSMR. CTSP is set to 0 or no CTS lost can occur. CTS LOST SIGNALED IN FRAME BD Figure 16-68. CTSx Lost in Synchronous Protocols Note: If the CTSS bit in the GSMR_H is set, all CTSx transitions must occur while the transmit clock is low. MOTOROLA MPC823e REFERENCE MANUAL 16-191...
Page 646 CDx lost error is recognized. Otherwise, the negation of CDx immediately causes the CDx lost condition to occur. Note: If the CDS bit in the GSMR_H is set, all CDx transitions must occur while the receive clock is low. 16-192 MPC823e REFERENCE MANUAL MOTOROLA...
Page 647 DPLL counter and begins DPLL operation. While the counter is counting, the DPLL monitors the incoming datastream for transitions and when a transition is detected, the DPLL makes a count adjustment to produce an output clock that tracks the incoming bits. MOTOROLA MPC823e REFERENCE MANUAL 16-193...
Page 648 Figure 16-70. DPLL Receiver Block Diagram TCLK HSTCLK TENC TDCR DPLL X1 MODE TEND TRANSMITTER HSTCLK TXEN HSTCLK ENCODED DATA SCCT DATA TINV TXDx HSTCLK X1 MODE TENC = NRZI Figure 16-71. DPLL Transmitter Block Diagram 16-194 MPC823e REFERENCE MANUAL MOTOROLA...
Page 649 (25MHz ÷ 8 = 3.125MHz). Thus, the frequency applied to the CLKx pin or generated by an internal baud rate generator may be up to 25MHz on a 25MHz MPC823e, if the DPLL 8x, 16x, or 32x options are used.
Page 650 • FM1—A one is represented by a transition at the beginning of the bit and another transition at the center of the bit. A zero is represented by a transition only at the beginning of the bit. 16-196 MPC823e REFERENCE MANUAL MOTOROLA...
Page 651 SCCx channel. Although you can either reset the SCCx receiver or transmitter or continue operation, the statistics on clock glitches must be kept for later evaluation. The glitch status indication can also be used as a debugging aid during the early phases of prototype testing. MOTOROLA MPC823e REFERENCE MANUAL 16-197...
Page 652 • Low speed mode—2.4Kb/s to 115.2Kb/s • Middle speed mode—0.576 Mb/s or 1.152 Mb/s • High speed mode—4 Mb/s Figure 16-73 illustrates how to implement a general infrared link with the MPC823e using an SCC, IrDA encoder/decoder module, and external IrDA transducer module. MPC823e...
Page 653 1. Clear the ENT bit in the GSMR_L. 2. Issue the INIT TX PARAMETERS command and make any additional modifications. 3. Set the ENT bit in the GSMR_L. MOTOROLA MPC823e REFERENCE MANUAL 16-199...
Page 654 3. Set the ENT and ENR bits in the GSMR_L and the serial communication controller is enabled with the new protocol. Tip: You can save power by clearing the ENT and ENR bits of the serial communication controllers. 16-200 MPC823e REFERENCE MANUAL MOTOROLA...
Page 655 RS-485, which defines a balanced line system allowing longer cables than RS-232 links. Synchronous protocols are sometimes defined to run over asynchronous links. Other protocols like Profibus extend the UART protocol to include LAN-oriented features such as token passing. MOTOROLA MPC823e REFERENCE MANUAL 16-201...
Page 656 • Received break character length indication • Programmable data length (5–8 bits) • Programmable 1 to 2 stop bits in transmission • Capable of reception without a stop bit • Programmable fractional stop bit length 16-202 MPC823e REFERENCE MANUAL MOTOROLA...
Page 657 When a complete byte has been clocked in, the contents of the shift register are transferred to a UART receive data buffer. If there is an error in this character, then the appropriate error bits are set by the communication processor module. MOTOROLA MPC823e REFERENCE MANUAL 16-203...
Page 658 NOTE: You are only responsible for initializing the items in bold. SCCx base = (IMMR & 0xFFFF0000) + 0x3D00 (SCC2) and 0x3E00 (SCC3). All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as a memory-based register. 16-204 MPC823e REFERENCE MANUAL MOTOROLA...
Page 659 • RCCM—This value is used to mask the comparison of the CHARACTER1 to CHARACTER 8 parameters so that classes of control characters can be defined. A one enables the bit comparison and a zero masks it. MOTOROLA MPC823e REFERENCE MANUAL 16-205...
Page 660 The latter option is useful when flow control characters such as XON or XOFF need to alert the core but do not belong to the received message. 16-206 MPC823e REFERENCE MANUAL MOTOROLA...
Page 661 When it is not in multidrop mode, it waits for the idle sequence (one character of idle) and does not lose any data that was in the receive FIFO when this command was executed. MOTOROLA MPC823e REFERENCE MANUAL 16-207...
Page 662 UADDR1 and UADDR2 and when a match is made, the AM bit in the buffer descriptor is set to indicate the matched address character and the data following it is written to the data buffers. Note: For characters less than 8 bits, the most-significant bits must be zero. 16-208 MPC823e REFERENCE MANUAL MOTOROLA...
Page 663 • • SCCX BASE+ 5E — — — — — — CHARACTER8 SCCX BASE+ 60 — — — — — — RCCM SCCX BASE + 62 — — — — — — — — RCCRP MOTOROLA MPC823e REFERENCE MANUAL 16-209...
Page 664 RCCRP and generates a maskable interrupt. The core must process the interrupt and read the RCCRP before a second control character arrives. If this does not occur, the SCCx UART controller overwrites the first control character. 16-210 MPC823e REFERENCE MANUAL MOTOROLA...
Page 665 These bits are reserved and must be set to 0. REA—Ready This bit is set by the core when the character is ready for transmission and remains 1 while the character is being transmitted. The communication processor module clears this bit after transmission. MOTOROLA MPC823e REFERENCE MANUAL 16-211...
Page 666 For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before the first character in the buffer. 16-212 MPC823e REFERENCE MANUAL MOTOROLA...
Page 667 0100 = Last transmitted stop bit 21/32. 0011 = Last transmitted stop bit 20/32. 0010 = Last transmitted stop bit 19/32. 0001 = Last transmitted stop bit 18/32. 0000 = Last transmitted stop bit 17/32. MOTOROLA MPC823e REFERENCE MANUAL 16-213...
Page 668 Note: Using the CTSx signal, the SCCx UART controller also offers an asynchronous flow control option that does not generate an error. Refer to the FLC bit description in Section 16.9.15.15 SCCx UART Mode Register for information about flow control. 16-214 MPC823e REFERENCE MANUAL MOTOROLA...
Page 669 The internal idle counter (IDLC) is reset every time a character is received. Note: To disable the idle sequence function, set the MAX_IDL value to zero. MOTOROLA MPC823e REFERENCE MANUAL 16-215...
Page 670 If the RZS bit is set in the PSMR–SCC UART register when the SCCx UART controller is in synchronous mode, then a break sequence is detected after only two successive break characters are received. 16-216 MPC823e REFERENCE MANUAL MOTOROLA...
Page 671 “don’t care” when they are transmitted. This field can be modified on-the-fly. 00 = 5 data bits. 01 = 6 data bits. 10 = 7 data bits. 11 = 8 data bits. MOTOROLA MPC823e REFERENCE MANUAL 16-217...
Page 672 A framing error is issued if a stop bit is missing, but a break status is only reported after back-to-back reception of two break characters without stop bits. 16-218 MPC823e REFERENCE MANUAL MOTOROLA...
Page 673 Note: You must set the P bit in the transmit buffer descriptor if you are using the MPC823e in multidrop UART mode. Bit 10—Reserved This bit is reserved and must be set to 0.
Page 674 Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. An example of the RX buffer descriptor process is illustrated in Figure 16-76. 16-220 MPC823e REFERENCE MANUAL MOTOROLA...
Page 675 POINTER 32-BIT BUFFER POINTER (MAX_IDL) WITH THIS BUFFER 10 CHARS 5 CHARS LONG IDLE PERIOD CHARACTERS RECEIVED BY UART PRESENT FOURTH CHARACTER TIME TIME HAS FRAMING ERROR! Figure 16-76. SCC2 UART Receive Buffer Descriptor Example MOTOROLA MPC823e REFERENCE MANUAL 16-221...
Page 676 The RX bit can cause an interrupt if it is enabled. C—Control Character 0 = This buffer does not contain a control character. 1 = This buffer contains a control character. The last byte in the buffer is one of the user-defined control characters. 16-222 MPC823e REFERENCE MANUAL MOTOROLA...
Page 677 This bit indicates that a character with a parity error has been received and located in the last byte of this buffer. A new receive buffer is used to receive more data. OV—Overrun This bit indicates that a receiver overrun has occurred while the SCCx UART controller was receiving a message. MOTOROLA MPC823e REFERENCE MANUAL 16-223...
Page 678 You are only responsible for initializing the items in bold. Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 16-224 MPC823e REFERENCE MANUAL MOTOROLA...
Page 679 This bit is only valid in multidrop mode. Either automatic or manual. 0 = This buffer only contains data. 1 = Set by the core, this bit indicates that this buffer contains address characters. All of the buffer data is transmitted as address characters. MOTOROLA MPC823e REFERENCE MANUAL 16-225...
Page 680 This field always points to the first location of the associated data buffer and can be even or odd. The buffer can reside in internal or external memory. The communication processor module writes these bits after it finishes transmitting the associated data buffer. 16-226 MPC823e REFERENCE MANUAL MOTOROLA...
Page 681 1. TX event assumes all seven characters were put into a single buffer and CR is set to 1 in the TX buffer descriptor. 2. The CTSx event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 16-77. SCCx UART Interrupt Event Example MOTOROLA MPC823e REFERENCE MANUAL 16-227...
Page 682 BRKE—Break End If set, this bit indicates that an end-of-break sequence has been found. This indication is set no sooner than after an idle bit is received following a break sequence. 16-228 MPC823e REFERENCE MANUAL MOTOROLA...
Page 683 1, the corresponding interrupt in the SCCE–UART register is enabled. If it is zero, the corresponding interrupt is masked. SCCM–UART FIELD RESERVED BRKE BRKS RESET ADDR (IMMR & 0xFFFF0000) + 0x MOTOROLA MPC823e REFERENCE MANUAL 16-229...
Page 684 000 and the T2CS field to 000. 5. Write 0x0001 to the SDCR to set the SDMA bus arbitration level to 5. 6. Connect the SCC2 to the NMSI and clear the SC2 bit in the SICR. 16-230 MPC823e REFERENCE MANUAL MOTOROLA...
Page 685 CTS2 pin, 8-bit characters, no parity, 1 stop bit, and asynchronous SCC2 UART operation. 26. Write 0x00028034 to the GSMR_L register to enable the SCC2 transmitter and receiver. This additional write ensures that the ENT and ENR bits are enabled last. MOTOROLA MPC823e REFERENCE MANUAL 16-231...
Page 686 S-records into data buffers and linking them to the transmit buffer table and it can be temporarily stopped when an XOFF character is received. This scheme minimizes the number of interrupts received by the core (one per S-record) and relieves it from the task of continually scanning for control characters. 16-232 MPC823e REFERENCE MANUAL MOTOROLA...
Page 687 HDLC mode, also called the SCCx HDLC controller, consists of separate transmit and receive sections whose operations are asynchronous with the core. You can allocate up to 196 buffer descriptors, so that you can transmit or receive many frames without interference from the host. MOTOROLA MPC823e REFERENCE MANUAL 16-233...
Page 688 I bit in the TX buffer descriptor is set. The SCCx HDLC controller then proceeds to the next TX buffer descriptor in the table. This method allows you to be interrupted after each buffer, a specific buffer, or each frame. 16-234 MPC823e REFERENCE MANUAL MOTOROLA...
Page 689 SCCx HDLC controller not to interrupt the core until a certain number of frames are received. You can combine this function with a timer to implement a timeout if less than the threshold number of frames are received. MOTOROLA MPC823e REFERENCE MANUAL 16-235...
Page 690 You are only responsible for initializing the items in bold. SCCx base = (IMMR & 0xFFFF0000) + 0x3D00 (SCC2) and 0x3E00 (SCC3). All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as a memory-based register. 16-236 MPC823e REFERENCE MANUAL MOTOROLA...
Page 691 When an address match is made, the address and the data following it are written into the data buffers. When the addresses are not matched and the frame is error-free, the nonmatching address received counter (NMARC) is incremented. MOTOROLA MPC823e REFERENCE MANUAL 16-237...
Page 692 GSMR_L. The SCCx HDLC controller uses the same data structure as other modes and it supports multibuffer operation and address comparisons. The reception errors are reported through the RX buffer descriptor and the transmit errors are reported through the TX buffer descriptor. 16-238 MPC823e REFERENCE MANUAL MOTOROLA...
Page 693 • INIT TX PARAMETERS—This command initializes all transmit parameters in this serial channel parameter RAM to their reset state and must only be issued when the transmitter is disabled. The INIT TX AND RX PARAMS command can be used to reset the transmit and receive parameters. MOTOROLA MPC823e REFERENCE MANUAL 16-239...
Page 694 36 bytes of data and 20 bytes of data if multiple buffers per frame are used. The channel also increments the retransmission counter. This requirement does not apply to small frames that consist of a single buffer. 16-240 MPC823e REFERENCE MANUAL MOTOROLA...
Page 695 Note: If you are using the data buffer swapping option, the above diagram refers to the last byte of the data buffer, not the last word. In SCCx-HDLC mode, the least- significant bit of each octet is transmitted first and the most-significant bit of the CRC is transmitted first. MOTOROLA MPC823e REFERENCE MANUAL 16-241...
Page 696 1 = Automatic frame retransmission is enabled. Retransmission only occurs if the lost CTSx occurs on the first or second buffer of the frame. Bits 7 and 13–15—Reserved These bits are reserved and must be set to 0. 16-242 MPC823e REFERENCE MANUAL MOTOROLA...
Page 697 This option, however, can improve the performance of HDLC transmissions of small back-to-back frames or in cases where you prefer to limit the number of flags transmitted between frames. The receiver is not affected by this bit. MOTOROLA MPC823e REFERENCE MANUAL 16-243...
Page 698 An example of the RX buffer descriptor process is illustrated in Figure 16-80. Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 16-244 MPC823e REFERENCE MANUAL MOTOROLA...
Page 699 UNEXPECTED ABORT TIME OCCURS BEFORE TIME CLOSING FLAG LEGEND: F = FLAG A = ADDRESS BYTE C = CONTROL BYTE I = INFORMATION BYTE CR = CRC BYTE Figure 16-80. SCC2 HDLC Receive Buffer Descriptor Example MOTOROLA MPC823e REFERENCE MANUAL 16-245...
Page 700 CD, OV, AB, and LG bits are set. The SCCx HDLC controller writes the number of frame octets to the DATA LENGTH field. 0 = This buffer is not the last one in a frame. 1 = This buffer is the last one in a frame. 16-246 MPC823e REFERENCE MANUAL MOTOROLA...
Page 701 This bit indicates that a receiver overrun has occurred while a frame was being received. CD—Carrier Detect Lost This bit indicates that a carrier detect signal has been negated while a frame was being received. This bit is only valid when working in NMSI mode. MOTOROLA MPC823e REFERENCE MANUAL 16-247...
Page 702 1 = The data buffer, which you have prepared, has not been transmitted or is currently being transmitted. You cannot write any fields of this buffer descriptor once this bit is set. Bits 1 and 7–13—Reserved These bits are reserved and must be set to 0. 16-248 MPC823e REFERENCE MANUAL MOTOROLA...
Page 703 If data from more than one buffer is currently in the FIFO when this error occurs, this bit is set in the currently open TX buffer descriptor. The SCCx HDLC controller writes these bits after it finishes transmitting the associated data buffer. MOTOROLA MPC823e REFERENCE MANUAL 16-249...
Page 704 SCCx HDLC controller sets the corresponding bit in this register. Interrupts generated by this register can be masked in the SCCM–HDLC register. An example of interrupts that can be generated using the HDLC protocol is illustrated in Figure 16-81. 16-250 MPC823e REFERENCE MANUAL MOTOROLA...
Page 705 1. TXB event shown assumes all three bytes were put into a single buffer. 2. Example shows one additional opening flag. This is programmable. 3. The CTSx event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 16-81. HDLC Interrupt Event Example MOTOROLA MPC823e REFERENCE MANUAL 16-251...
Page 706 It is set immediately if no frame was in progress when the command was issued. TXE—TX Error This bit indicates that an error has occurred on the transmitter channel. 16-252 MPC823e REFERENCE MANUAL MOTOROLA...
Page 707 1, the corresponding interrupt in the SCCE–HDLC register is enabled. If the bit is zero, the corresponding interrupt in the SCCE–HDLC is masked. SCCM–HDLC FIELD RESERVED GLT DCC FLG GRA RESERVED TXE RESET ADDR (IMMR & 0xFFFF0000) + 0xA34 MOTOROLA MPC823e REFERENCE MANUAL 16-253...
Page 708 This bit is set when the RXDx pin is a logic one for 15 or more consecutive bit times. It is cleared after a single logic zero is received. 0 = The RXDx pin is busy. 1 = The RXDx pin is idle. 16-254 MPC823e REFERENCE MANUAL MOTOROLA...
Page 709 19. Initialize the TX buffer descriptor. Assume the TX data frame is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status, 0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer. 20. Write 0xFFFF to the SCCE–HDLC to clear any previous events. MOTOROLA MPC823e REFERENCE MANUAL 16-255...
Page 710 16-bit CCITT-CRC. Multiple frames in the FIFO are not allowed in this example. 5. Write 0x004AA430 to the GSMR_L to enable the SCC2 transmitter and receiver. This additional write ensures that the ENT and ENR bits are enabled last. 16-256 MPC823e REFERENCE MANUAL MOTOROLA...
Page 711 Where collisions are concerned, these protocols use the bus efficiently because one station is always able to complete its transmission. Once a station completes a transmission, it lowers its own priority to give other devices fair access to the physical connection. MOTOROLA MPC823e REFERENCE MANUAL 16-257...
Page 712 1. Transceivers may be used to extend the LAN size, if necessary. 2. The TXDx pins of slave devices must be configured to open-drain in the port C parallel I/O port. Figure 16-82. Typical HDLC Bus Multimaster Configuration 16-258 MPC823e REFERENCE MANUAL MOTOROLA...
Page 713 • Superset of the SCCx in HDLC mode • Automatic HDLC bus access • Automatic retransmission in case of a collision • May be used with the NMSI mode or a TDM bus • Delayed RTSx mode MOTOROLA MPC823e REFERENCE MANUAL 16-259...
Page 714 If the source address is included in the HDLC frame and destination address, a predefined priority of nodes results. Collisions can be detected no later than the end of the source address, if one is included. Note: The HDLC bus can be used with many different HDLC-based frame formats. 16-260 MPC823e REFERENCE MANUAL MOTOROLA...
Page 715 TCLK TXDx (Output) CTSx (Input) CTSx sampled at three quarter point. Collision detected when TXDx=1, but CTSx=0. Figure 16-85. Example of a Nonsymmetrical Duty Cycle MOTOROLA MPC823e REFERENCE MANUAL 16-261...
Page 716 Normally, the RTSx pin goes active at the beginning of the opening flag’s first bit. Although using the RTSx pin is not required, there is a mode on the MPC823e HDLC bus that delays the RTSx signal by one bit. This mode is selected with the BRM bit in the PSMR–SCC HDLC register.
Page 717 2. The TSA in the serial interface of each station is used to configure the preferred time-slot. 3. You can choose the number of stations to share a time-slot. In this example, two are used. Figure 16-88. HDLC Bus Time-Slot Assigner Transmission Line Configuration MOTOROLA MPC823e REFERENCE MANUAL 16-263...
Page 718 16.9.17.3 HDLC BUS MEMORY MAP AND PROGRAMMING.The HDLC bus on the MPC823e is implemented using the SCCx in HDLC mode with certain bits set. If you want to do otherwise, see Section 16.9.16.5 Programming the SCCs in HDLC Mode for information about HDLC mode programming.
Page 719 LocalTalk refers to an HDLC-based link and physical layer protocol that runs at the rate of 230.4kbps. In this manual, the term AppleTalk controller refers to a support that the MPC823e provides for the LocalTalk protocol. The AppleTalk controller provides the required frame synchronization, bit sequence, preamble, and postamble onto standard HDLC frames.
Page 720 • Automatic postamble transmission • Reception of sync sequence does not cause extra CDx interrupts • Reception is automatically disabled while transmitting a frame • Transmit-on-demand feature that expedites frames • Connects directly to an RS-422 transceiver 16-266 MPC823e REFERENCE MANUAL MOTOROLA...
Page 721 3.686MHz frequency. The MPC823e asserts the RTSx signal throughout the duration of the frame so that RTSx can be used to enable the RS-422 transceiver.
Page 722 3. Set the DRT bit to 1. 4. Set all other bits to 0 or default. Use the transmit-on-demand register described in Section 16.9.5 Transmit-on-Demand Register to expedite a transmit frame by setting the TOD bit to 1. 16-268 MPC823e REFERENCE MANUAL MOTOROLA...
Page 723 R bit. If the I bit is set, the controller sets the TXB bit in the SCCE–ASYNC HDLC register. Thus, the I bit can be used to generate an interrupt after each buffer, after a group of buffers, or after each complete frame has been transmitted. MOTOROLA MPC823e REFERENCE MANUAL 16-269...
Page 724 The SCCx ASYNC HDLC controller then waits for the start of the next frame which may or may not have an opening flag. 16-270 MPC823e REFERENCE MANUAL MOTOROLA...
Page 725 • Reverses the transmission transparency sequence by discarding a received control-escape character (0x7D) and exclusive-OR’ing the following byte with 0x20 before performing the CRC calculation and writing the byte into memory. MOTOROLA MPC823e REFERENCE MANUAL 16-271...
Page 726 XOR_NEXT ? CHAR ≥= CLOSING CHAR ≥= CTRL ESC? FLAG ? XOR_NEXT=1 CHAR ⊕ 0X20 CHAR ≥= CLOSING EXIT XOR_NEXT =0 FLAG ? WRITE CHAR TO BUFFER END OF FRAME EXIT ABORT Figure 16-92. Reception Flowchart 16-272 MPC823e REFERENCE MANUAL MOTOROLA...
Page 727 HDLC register so that bits 2 and 3 are set to 1 for proper operation. • Time-Fill (Idling)—When transmitting, the SCCx ASYNC HDLC controller transmits IDLE characters when no data is available for transmission. When receiving, the SCCx ASYNC HDLC controller ignores IDLE characters. MOTOROLA MPC823e REFERENCE MANUAL 16-273...
Page 728 • ZERO—You must set this field to zero. • RFTHR—The received frames threshold indicates how many frames are received before the RXF bit is set in the SCCE–ASYNC HDLC register. 16-274 MPC823e REFERENCE MANUAL MOTOROLA...
Page 729 OxO4 OxO3 OxO2 OxO1 OxOO • NOF—This entry must be initialized to the number of opening flags to be transmitted at the beginning of a frame. A value of n corresponds to n +1 flags. MOTOROLA MPC823e REFERENCE MANUAL 16-275...
Page 730 01 = 8 × clock mode (do not use for IrLAP). 10 = 16 × clock mode. 11 = 32 × clock mode (do not use for IrLAP). The data synchronization register (DSR) is reserved in asynchronous HDLC mode. It must be set to 0x7E7E. 16-276 MPC823e REFERENCE MANUAL MOTOROLA...
Page 731 TBPTR entry in the SCCx parameter RAM table. However, no new buffer descriptor is accessed for this channel. Note: Unlike the other MPC823e protocols, the SCCx ASYNC HDLC controller does not flush the FIFO because of the STOP TRANSMIT command. A maximum of 32 characters can be transmitted before an abort sequence.
Page 732 The CRC error status condition is not checked on aborted frames. If the abort sequence is received and no frame is currently being received, the next buffer descriptor is opened and then closed with the AB bit set. 16-278 MPC823e REFERENCE MANUAL MOTOROLA...
Page 733 No characters, except idles, are transmitted while CTS is negated. Bits 1 and 4–15—Reserved These bits are reserved and must be set to 0. CHLN—Character Length For asynchronous HDLC and IrLAP modes, these bits must be set to 1. MOTOROLA MPC823e REFERENCE MANUAL 16-279...
Page 734 RBASE points to in the table. The number of RX buffer descriptors in this table are programmable and determined only by the W bit and overall space constraints of the dual-port RAM. 16-280 MPC823e REFERENCE MANUAL MOTOROLA...
Page 735 CR—RX CRC Error This bit indicates that this frame contains a CRC error. The received CRC bytes are always written to the receive buffer. OV—Overrun This bit indicates that a receiver overrun has occurred during frame reception. MOTOROLA MPC823e REFERENCE MANUAL 16-281...
Page 736 You are only responsible for initializing the items in bold. Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 16-282 MPC823e REFERENCE MANUAL MOTOROLA...
Page 737 FIFO when this error occurs, this bit is set in the currently open TX buffer descriptor. These bits are written by the SCCx ASYNC HDLC controller after it finishes transmitting the associated data buffer. MOTOROLA MPC823e REFERENCE MANUAL 16-283...
Page 738 If set, this bit indicates that a serial communication controller has found a glitch on the receive clock. GLT—Glitch on TX If set, this bit indicates that a serial communication controller has found a glitch on the transmit clock. 16-284 MPC823e REFERENCE MANUAL MOTOROLA...
Page 739 FIFO. RXB—RX Buffer This bit indicates that a buffer (that is not the last in the frame with its I bit set) has been received over the SCCx ASYNC HDLC channel. MOTOROLA MPC823e REFERENCE MANUAL 16-285...
Page 740 9. Write the MRBLR with the maximum receiver buffer size. 10. Write C_MASK and C_PRES with the standard values. 11. Write the ZERO register to 0x0000. 12. Program the RFTHR to the number of frames that must be received before an interrupt is generated. 16-286 MPC823e REFERENCE MANUAL MOTOROLA...
Page 741 IR OUT ENCODER DRIVER&LED ENCODER/ TRANSDUCER DECODER SCC2 MODULE MODULE IR RECEIVE DETECTOR IR IN DECODER & RECEIVER RXD2 Figure 16-93. Serial IrDA Link Note: Serial communication controller 3 (SCC3) does not operate in IrDA mode. MOTOROLA MPC823e REFERENCE MANUAL 16-287...
Page 742 (minus a protocol-defined tolerance). The maximum pulse duration is of the bit duration (plus a protocol-defined tolerance). UART FRAME START STOP DATA BITS INFRA- RED FRAME 3/16 BIT TIME Figure 16-94. Low-Speed IrDA Data Format 16-288 MPC823e REFERENCE MANUAL MOTOROLA...
Page 743 Figure 16-96. For 0.576 and 1.152Mb/s, the minimum and maximum pulse duration are the nominal of the bit duration (plus or minus the protocol-defined tolerance). DATA BITS 1/4 BIT TIME Figure 16-96. Middle-Speed IrDA Data Format MOTOROLA MPC823e REFERENCE MANUAL 16-289...
Page 744 The following table defines the chip pattern representation of the four unique data symbols defined for 4PPM. DATA BIT PAIR 4PPM DATA SYMBOL 1000 0100 0010 0001 16-290 MPC823e REFERENCE MANUAL MOTOROLA...
Page 745 After the start flag is received, the receiver can begin interpreting the data symbols in the link layer frame. The start flag consists of exactly one transmission of the following stream of symbols. 0000 1100 0000 1100 0110 0000 0110 0000 Figure 16-100. Start Flag Symbol Format MOTOROLA MPC823e REFERENCE MANUAL 16-291...
Page 746 STA, and STO—are transmitted as is. The link layer frame bits are encoded before transmission. Each two bits encoded into four chips according to the 4PPM scheme. DATA BITS 1/4 BIT TIME Figure 16-102. High-Speed IrDA Data Format 16-292 MPC823e REFERENCE MANUAL MOTOROLA...
Page 747 • By the Timer 2 expiration when you set the TS bit in the IRSIP register. You are responsible for creating the appropriate SIP waveform by writing the proper values to the SLL and SHL fields of the IRSIP register. MOTOROLA MPC823e REFERENCE MANUAL 16-293...
Page 748 This bit determines the polarity of the transmitted signal. 0 = Active high polarity. An active high pulse is encoded as 0. 1 = Active low polarity. An active low pulse is encoded as 0. 16-294 MPC823e REFERENCE MANUAL MOTOROLA...
Page 749 0 = IrDA is disabled. 1 = IrDA is enabled. Note: Changing the EN bit value is allowed only when the SCC2 is off (after the ENR and ENT bits in the GSMR_L are cleared). MOTOROLA MPC823e REFERENCE MANUAL 16-295...
Page 750 Program this field with the width of the SIP assertion part (in bit rate clock units). SLL—Serial Infrared Interaction Pulse Low-Level Length Program this field with the width of the SIP negation part (in bit rate clock units). 16-296 MPC823e REFERENCE MANUAL MOTOROLA...
Page 751 21. Write 0x0001 to the IRMODE register to enable low-speed infra-red. 22. Set the PSMR–SCC ASYNC HDLC register appropriately. 23. Turn on the transmitter and receiver in the GSMR_L by setting the ENT and ENR bits. MOTOROLA MPC823e REFERENCE MANUAL 16-297...
Page 752 18. Initialize the TX buffer descriptor. Assume the TX data frame is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status. Write 0x0005 to TX_BD_Length. Write 0x00002000 to TX_BD_Pointer. 19. Write 0xFFFF to the SCCE–HDLC to clear any previous events. 16-298 MPC823e REFERENCE MANUAL MOTOROLA...
Page 753 Once a complete frame is received, the RX buffer descriptor is closed. Any data received after 256 bytes or a single frame causes a busy (out-of-buffers) condition since only one RX buffer descriptor is prepared. MOTOROLA MPC823e REFERENCE MANUAL 16-299...
Page 754 Mode. The SCC2 and infrared registers must be initialized. The following list is an initialization sequence for a high-speed infrared channel. The transmitter and receiver are both enabled. Both transmit and receive clocks are provided externally to MPC823e using the CLK3 pin.
Page 755 By appropriately setting the GSMR_L, the SCCx channels can be configured to function in Transparent mode. The MPC823e receives and transmits the entire serial bitstream transparently. This mode is configured by selecting the TTX and TRX bits in the GSMR_H for the transmitter and receiver, respectively.
Page 756 Failure to provide the next buffer in time results in a transmit underrun, thus causing the TXE bit in the SCCE–Transparent register to be set. 16-302 MPC823e REFERENCE MANUAL MOTOROLA...
Page 757 (called receive synchronization ) must occur before data can be received. You can have bit-level control of the synchronization process when receiving and transmitting by using either an inline synchronization pattern or external synchronization signals. MOTOROLA MPC823e REFERENCE MANUAL 16-303...
Page 758 DSR–SCC TRANSPARENT (SYNL = 10) FIELD 8-BIT SYNC RESET ADDR (IMMR & 0xFFFF0000) + 0xA2E NOTE: X = “Don’t Care”. DSR–SCC TRANSPARENT (SYNL = 11) FIELD 16-BIT SYNC RESET ADDR (IMMR & 0xFFFF0000) + 0xA2E 16-304 MPC823e REFERENCE MANUAL MOTOROLA...
Page 759 CDS and CTCC bits of the GSMR_H control the sampling option. You can also link the transmitter synchronization to the receiver synchronization. The pulse/envelope and sampling options are described in Section 16.9.10 Controlling SCCx Timing. MOTOROLA MPC823e REFERENCE MANUAL 16-305...
Page 760 3. The transparent frame contains a CRC if the TC bit is set in the TX buffer descriptor. Figure 16-104. Sending Transparent Frames Between Each MPC823e MPC823e A and B in Figure 16-105 exchange transparent frames and synchronize each other using the RTSx and CDx pins. However, the CTSx pin is not required since transmission begins at any time.
Page 761 64 additional bits and the transmit FIFO is flushed. The TBPTR is not advanced, no new buffer descriptor is accessed and no new buffers are transmitted for this channel. The transmitter will send idles. MOTOROLA MPC823e REFERENCE MANUAL 16-307...
Page 762 RAM to their reset state and must only be issued when the receiver is disabled. The INIT TX AND RX PARAMS command can also be used to reset the receive and transmit parameters. 16-308 MPC823e REFERENCE MANUAL MOTOROLA...
Page 763 GSMR_H, the PSMR is not used by the SCCx Transparent controller. If transparent mode is only selected for the transmitter/receiver, then the transmitter/receiver can be programmed to support another protocol. In such a case, you can use the PSMR for the other protocol. MOTOROLA MPC823e REFERENCE MANUAL 16-309...
Page 764 Once the E bit is set, the core must not write any fields of this RX buffer descriptor. Bits 1, 7, 9–10, and 12—Reserved These bits are reserved and must be set to 0. 16-310 MPC823e REFERENCE MANUAL MOTOROLA...
Page 765 In decoding modes, where a transition occurs on every bit, the DPLL error is set when a missing transition occurs. NO—RX Non-Octet This bit indicates that a frame containing a number of bits not exactly divisible by eight is received. MOTOROLA MPC823e REFERENCE MANUAL 16-311...
Page 766 You are only responsible for initializing the items in bold. Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 16-312 MPC823e REFERENCE MANUAL MOTOROLA...
Page 767 However, the R bit is cleared if an error occurs during transmission, regardless of how the CM bit is set. MOTOROLA MPC823e REFERENCE MANUAL 16-313...
Page 768 Bits 0–2, 6–7, and 9–10—Reserved These bits are reserved and must be set to 0. GLR—Glitch on RX If set, this bit indicates that a serial communication controller has found a glitch on the receive clock. 16-314 MPC823e REFERENCE MANUAL MOTOROLA...
Page 769 RXDx pin. The I bit in the receive buffer descriptor must be set in order to get an update of this bit. MOTOROLA MPC823e REFERENCE MANUAL 16-315...
Page 770 These bits are reserved and must be set to 0. CS—Carrier Sense (DPLL) This bit shows the real-time internal CSx signal, as determined by the DPLL. 0 = The DPLL does not sense a carrier. 1 = The DPLL senses a carrier. 16-316 MPC823e REFERENCE MANUAL MOTOROLA...
Page 771 They implement the connection illustrated on MPC823e (B) in Figure 16-105. The transmit and receive clocks are externally provided to MPC823e (B) using the CLK3 pin. The SCC2 Transparent controller is configured with the RTS2 and CD2 pins active and CTS2 is grounded internally by the configuration in port C.
Page 772 Ethernet. This has limited the length of the data portion of the frame to 1,500 bytes and the total frame length to 1,518 bytes. The last 4 bytes of the frame are the frame check sequence (FCS), which is the standard 32-bit CCITT-CRC polynomial used in many other protocols. 16-318 MPC823e REFERENCE MANUAL MOTOROLA...
Page 773 15 retries, an error occurs. The 10Mbps Ethernet provides 0.8µs per byte. The preamble plus start frame delimiter is transmitted in 6.4µs. The minimum interframe gap is 9.6µs and the slot time is 52µs. Therefore, you must operate the MPC823e at a minimum frequency of 20MHz to implement Ethernet.
Page 774 Communication Processor Module 16.9.22.2 ETHERNET ON THE MPC823e. When the MODE field in the general SCCx mode low register (GSMR_L) selects an SCCx to be in Ethernet mode, the serial communication controllers perform the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions.
Page 775 SCCs in Ethernet mode. It is important that first-time users of the MPC823e who plan to use Ethernet read the following sections of this manual first.
Page 776 STORED IN RECEIVE BUFFER NOTE: The MPC82x automatically pads the short transmit frames. Figure 16-107. Connecting the MPC823e to Ethernet The following pins function differently when a serial communication controller is in Ethernet mode than when it is in other protocols: •...
Page 777 MPC823e can perform external loopback testing. This can be controlled by any available parallel I/O pin on the MPC823e. The passive components that are needed to connect to AUI or twisted-pair media are external to the EEST.
Page 778 The receiver can receive physical (individual), group (multicast), and broadcast addresses. SCCx Ethernet reception frame data is not written to memory until the internal address recognition algorithm is complete, which improves bus utilization with frames not addressed to this station. 16-324 MPC823e REFERENCE MANUAL MOTOROLA...
Page 779 RX buffer descriptor, and clears the E bit. Then it generates a maskable interrupt, which indicates that a frame has been received and is in memory. The SCCx Ethernet controller then waits for a new frame. It receives serial data least-significant bit first. MOTOROLA MPC823e REFERENCE MANUAL 16-325...
Page 780 Half-word Persistence SCCx Base + 7A RFBD_PTR Half-word RX First Buffer Descriptor Pointer SCCx Base + 7C TFBD_PTR Half-word TX First Buffer Descriptor Pointer SCCx Base + 7E TLBD_PTR Half-word TX Last Buffer Descriptor Pointer 16-326 MPC823e REFERENCE MANUAL MOTOROLA...
Page 781 16-bit register. This value is typically 0xF. If the frame is not transmitted after this limit is reached, an interrupt can be generated. • RET_CNT is a temporary down-counter used to count the number of retries. MOTOROLA MPC823e REFERENCE MANUAL 16-327...
Page 782 Ethernet channel is enabled to disable all group hash address recognition functions. The SET GROUP ADDRESS command is used to enable the hash table. • TBUF0_DATA0—For internal use only. • TBUF0_DATA1—For internal use only. • TBUF0_RBA0—For internal use only. 16-328 MPC823e REFERENCE MANUAL MOTOROLA...
Page 783 After placing an address in TADDR, you must issue the SET GROUP ADDRESS command. TADDR_L is the lowest order half-word, TADDR_H is the highest order half-word and TADDR_M is the middle half-word. MOTOROLA MPC823e REFERENCE MANUAL 16-329...
Page 784 Note: Before issuing a CPM reset (RST bit in the CPCR), configure the TENA pin as an input. • STOP TRANSMIT —When used with the SCCx Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE 802.3 station. It must not be used. 16-330 MPC823e REFERENCE MANUAL MOTOROLA...
Page 785 RAM to their reset state and must only be issued when the receiver is disabled. The INIT TX AND RX PARAMS command can also be used to reset the receive and transmit parameters. MOTOROLA MPC823e REFERENCE MANUAL 16-331...
Page 786 In the physical type of address recognition, the SCCx Ethernet controller compares the destination address field of the received frame with the physical address that you program in PADDR1_H, PADDR1_M, and PADDR1_L. You can also perform address recognition on multiple individual addresses using the IADDR1–4 hash table. 16-332 MPC823e REFERENCE MANUAL MOTOROLA...
Page 787 RECEIVE FRAME IGNORE RRJCT PIN RECEIVE FRAME IGNORE MATCH ? RRJCT PIN RECEIVE FRAME IGNORE RRJCT PIN PROMISC ? START RECEIVE DISCARD FRAME IF RRJCT PIN IS DISCARD FRAME ASSERTED Figure 16-108. Ethernet Address Recognition Flowchart MOTOROLA MPC823e REFERENCE MANUAL 16-333...
Page 788 Note: The hash tables cannot be used to reject frames that match a set of entered addresses because unintended addresses are matched to the same bit in the hash table. 16-334 MPC823e REFERENCE MANUAL MOTOROLA...
Page 789 HBC bit in the PSMR–SCC Ethernet must be zero. In external loopback operation, the SCCx Ethernet controller listens for data received from the EEST at the same time that it is transmitting. MOTOROLA MPC823e REFERENCE MANUAL 16-335...
Page 790 This is called the heartbeat condition. If the HBC bit is set in the PSMR–SCC Ethernet and the MPC823e does not detect a heartbeat condition after transmitting a frame, then a heartbeat error occurs. In which case, the channel closes the buffer, sets the HB bit in the TX buffer descriptor, and generates a TXE interrupt if it is enabled.
Page 791 FC—Force Collision 0 = Normal operation. 1 = The channel forces a collision when each frame is transmitted. The MPC823e must be configured in loopback operation when using this feature so that you can test the collision logic. In the end, the retry limit for each transmit frame is exceeded.
Page 792 LCW—Late Collision Window 0 = A late collision is any collision that occurs at least 64 bytes from the preamble. 1 = A late collision is any collision that occurs at least 56 bytes from the preamble. 16-338 MPC823e REFERENCE MANUAL MOTOROLA...
Page 793 111 = Begin searching for the SFD 24 bits after the assertion of RENA. FDE—Full-Duplex Ethernet 0 = Disable full-duplex Ethernet mode. 1 = Enable full-duplex Ethernet mode. Note: When this bit is set to 1, you must also set the LPB bit to 1. MOTOROLA MPC823e REFERENCE MANUAL 16-339...
Page 794 XXXX BUFFER 64 BYTES EMPTY STILL EMPTY POINTER 32-BIT BUFFER POINTER NON-COLLIDED ETHERNET FRAME 1 FRAME 2 LINE IDLE TWO FRAMES PRESENT RECEIVED IN ETHERNET TIME COLLISION TIME Figure 16-109. Ethernet Receive Buffer Descriptor Example 16-340 MPC823e REFERENCE MANUAL MOTOROLA...
Page 795 0 = No interrupt is generated after this buffer is used. 1 = The RXB or RXF bit of the SCCE–Ethernet register is set when this buffer is used by the SCCx Ethernet controller. These two bits can cause interrupts if they are enabled. MOTOROLA MPC823e REFERENCE MANUAL 16-341...
Page 796 This bit is only set if a late collision occurs or if the RSH bit is enabled in the PSMR–SCC Ethernet. Late collisions are better defined in the LCW bit of the same register. 16-342 MPC823e REFERENCE MANUAL MOTOROLA...
Page 797 1 = The data buffer, which you have prepared for transmission, has not been transmitted or is currently being transmitted. You cannot write any fields of this buffer descriptor once this bit is set. MOTOROLA MPC823e REFERENCE MANUAL 16-343...
Page 798 This bit indicates the collision input was not asserted within 20 transmit clocks after transmission. It cannot be set unless the HBC bit is set in the PSMR–SCC Ethernet. The SCCx Ethernet controller writes this bit after it finishes transmitting the associated data buffer. 16-344 MPC823e REFERENCE MANUAL MOTOROLA...
Page 799 This field contains the address of the associated data buffer, can be even or odd, and reside in internal or external memory. This value is never modified by the communication processor module. The SCCx Ethernet controller writes these bits after it finishes transmitting the associated data buffer. MOTOROLA MPC823e REFERENCE MANUAL 16-345...
Page 800 This bit indicates that an error has occurred on the transmitter channel. RXF—RX Frame This bit indicates that a complete frame has been received on the Ethernet channel. BSY—Busy Condition This bit indicates when a frame is received and discarded due to a lack of buffers. 16-346 MPC823e REFERENCE MANUAL MOTOROLA...
Page 801 2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission. 3. The TENA or CLSN events, if required, must be programmed in the port C parallel I/O, not in the SCC itself. Figure 16-110. Ethernet Interrupt Events Example MOTOROLA MPC823e REFERENCE MANUAL 16-347...
Page 802 TX buffer descriptor in the dual-port RAM. Assuming one RX buffer descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008. 16-348 MPC823e REFERENCE MANUAL MOTOROLA...
Page 803 28. Write 0x001A to the SCCM–Ethernet to enable the TXE, RXF, and TXB interrupts. 29. Write 0x20000000 to the CIMR so that SCC2 can generate a system interrupt. The CICR must also be initialized. 30. Write 0x00000000 to the GSMR_H to enable normal operation of all modes. MOTOROLA MPC823e REFERENCE MANUAL 16-349...
Page 804 The universal serial bus (USB) is an industry standard extension to the PC architecture. The USB controller allows the MPC823e to exchange data with a PC host. It supports data exchanges between a host computer and a wide range of simultaneously accessible peripherals.
Page 805 PORT CONTROL TX DATA FIFO MODE REGISTER COMMAND REGISTER RX FIFO PORT CONFIGURATION ADDRESS USB FUNCTION ENDPOINT REGISTER AND HOST STATE MACHINES ENDPOINT REGISTERS RECEIVER TRANSMITTER DPLL/ INTERFACE EXTERNAL TRANSCEIVER Figure 16-111. USB Controller Block Diagram MOTOROLA MPC823e REFERENCE MANUAL 16-351...
Page 806 • Generation and transmission of SOF token every 1ms. • Scheduling the various transfers within frame and between frames. • The MPC823e USB host controller does not integrate the root hub. An external hub is required when more than one device is connected to the host.
Page 807 There are six I/O port pins associated with the USB port and their functionality is described in Table 16-31. Some transceivers may need additional control lines (speed select or low-power control), which can be supported by the general-purpose output lines. MOTOROLA MPC823e REFERENCE MANUAL 16-353...
Page 808 DPLL circuitry to recover the bit rate clock. Refer to Section 16.7.5.3 Serial Interface Clock Route Register for more information. Note: The MPC823e can run at different frequencies, but the USB reference clock must be four times the USB bit rate. The reference clock must be 48MHz for a 12Mb full-speed transfer or 6MHz for a 1.5Mb low-speed transfer.
Page 809 (the PID or CRC check fails or the packet length is not 3 bytes) are ignored. RESET UNENUMERATED ENUMERATION PROCESS IDLE SETUP TOKEN TOKEN TOKEN TOKEN SETUP TRANSMIT RECEIVE Figure 16-113. USB Controller Operating Modes MOTOROLA MPC823e REFERENCE MANUAL 16-355...
Page 810 ACK. If the RHS field is programmed to respond with STALL, a STALL handshake is returned. In both cases, the buffer will receive the data packet if the buffer descriptors are available. 16-356 MPC823e REFERENCE MANUAL MOTOROLA...
Page 811 If a reception error occurred, no handshake packet will be returned and the error status bits will be set in the last buffer descriptor associated with this packet. MOTOROLA MPC823e REFERENCE MANUAL 16-357...
Page 812 NOTE: You are only responsible for initializing the items in bold. USB Base = (IMMR & 0xFFFF0000) + 0x3C00. All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as a memory-based register. 16-358 MPC823e REFERENCE MANUAL MOTOROLA...
Page 813 The entry contains 11 bits representing the frame number. An SOF interrupt is issued when this entry is updated. You must initialize this parameter to zero before operating the USB controller. FRAME_N FIELD RESERVED FRAME NUMBER RESET ADDR USB BASE + 0x10 MOTOROLA MPC823e REFERENCE MANUAL 16-359...
Page 814 USB controller. Furthermore, you must not configure buffer descriptor tables of the USB to overlap any other serial channel’s buffer descriptors or erratic operation will occur. Note: RBASE and TBASE must contain a value that is divisible by eight. 16-360 MPC823e REFERENCE MANUAL MOTOROLA...
Page 815 • MRBLR—The maximum receive buffer length register defines the maximum number of bytes that the MPC823e will write to the USB receive buffer before moving to the next buffer. MRBLR must be divisible by four. The MPC823e can write fewer bytes to the buffer than the MRBLR value if a condition such as an error or end-of-packet occurs, but it will never write more bytes than the MRBLR value.
Page 816 SDMA channels. RX internal byte count (RBCNT) is a down-count value that is initialized with the MRBLR value and decremented with every byte written by the SDMA channels. RSTATE, TSTATE, RTEMP, TTEMP, and the reserved areas are only used by the RISC microcontroller. 16-362 MPC823e REFERENCE MANUAL MOTOROLA...
Page 817 100 = Reserved. 101 = Reserved. 110 = Reserved. 111 = Reserved. • ENDPOINT—This bit is the logical pipe number. 00 = Endpoint 0. 01 = Endpoint 1. 10 = Endpoint 2. 11 = Endpoint 3. MOTOROLA MPC823e REFERENCE MANUAL 16-363...
Page 818 RX buffer descriptor and the RXB bit in the USB event register. In isochronous mode, the USB controller reports a CRC error, however, there are no handshake packets (ACK) and the transfer continues normally when an error occurs. 16-364 MPC823e REFERENCE MANUAL MOTOROLA...
Page 819 0 = The USB controller implements a USB function. 1 = The USB controller implements a USB host. Endpoint 0 operates as the host. The other endpoints are not used, unless the TEST bit is set. MOTOROLA MPC823e REFERENCE MANUAL 16-365...
Page 820 The third and fourth words contain a pointer that always points to the beginning of the received data buffer. OFFSET + 0 OFFSET + 2 DATA LENGTH OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. 16-366 MPC823e REFERENCE MANUAL MOTOROLA...
Page 821 USB controller after the received data has been placed into the associated data buffer. 0 = This buffer does not contain the first byte of the message. 1 = This buffer contains the first byte of the message. MOTOROLA MPC823e REFERENCE MANUAL 16-367...
Page 822 RX DATA BUFFER POINTER This field always points to the first location of the associated data buffer and must be divisible by four. The buffer may reside in either internal or external memory. 16-368 MPC823e REFERENCE MANUAL MOTOROLA...
Page 823 0 = No interrupt is generated after this buffer has been serviced. 1 = The TXB or TXEx bit in the USB event register is set when this buffer is serviced. TXB and TXEx can cause interrupts if they are enabled. MOTOROLA MPC823e REFERENCE MANUAL 16-369...
Page 824 This bit indicates that the endpoint has responded with a NAK handshake. The packet was received error-free, however, the endpoint could not accept it. This bit is written by the USB controller after it has finished transmitting the associated data buffer. 16-370 MPC823e REFERENCE MANUAL MOTOROLA...
Page 825 USADR FIELD RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0xA01 Bit 0—Reserved This bit is reserved and must be set to 0. SAD—Slave Address 0–6 This field contains the slave address for the USB port. MOTOROLA MPC823e REFERENCE MANUAL 16-371...
Page 826 Section 16.10.6 USB Commands for more information). The FLUSH bit is always read as a zero. Bits 2–5—Reserved These bits are reserved and must be set to zero. EP—Endpoint This field selects one of the four supported endpoints. 16-372 MPC823e REFERENCE MANUAL MOTOROLA...
Page 827 1 = Automatic frame retransmission is enabled. The frame is retransmitted if a transmit an error occurred (time-out). Note: The RTE bit can only be set if the transmit packet is contained in a single buffer. Otherwise, retransmission must be handled by software intervention. MOTOROLA MPC823e REFERENCE MANUAL 16-373...
Page 828 The actual buffers can reside in either external or internal memory. Data buffers can reside in the parameter RAM of a serial communication controller if it is not enabled. 16-374 MPC823e REFERENCE MANUAL MOTOROLA...
Page 829 EP0 RX BD TABLE POINTER EP0 TX BD TABLE POINTER FRAME STATUS DATA LENGTH RX DATA BUFFER EP3 RX BD DATA POINTER TABLE POINTER EP3 TX BD TABLE POINTER Figure 16-114. USB Buffer Descriptor Ring MOTOROLA MPC823e REFERENCE MANUAL 16-375...
Page 830 0) or after the last character was transmitted on the line ( L is set to 1). RXB—RX Buffer This bit indicates that a buffer has been received. It is set after the last character has been written to the receive buffer and the RX buffer descriptor is closed. 16-376 MPC823e REFERENCE MANUAL MOTOROLA...
Page 831 When set, this bit indicates that an idle condition has been detected on the USB lines. It is cleared when the bus is not idle. Software has to set up a timer to detect the idle state that occurs after 3ms. MOTOROLA MPC823e REFERENCE MANUAL 16-377...
Page 832 17. Write FACEFACE to DPRAM+210 to set up the endpoint 1 TX data pattern. 18. Write BACEBACE to DPRAM+220 to set up the endpoint 2 TX data pattern. 19. Write CACECACE to DPRAM+230 to set up the endpoint 3 TX data pattern. 16-378 MPC823e REFERENCE MANUAL MOTOROLA...
Page 833 38. Write 0x82 to the USCOM to start filling the TX FIFO with endpoint 2 data ready for transmission when IN token is received. 39. Write 0x83 to the USCOM to start filling the TX FIFO with endpoint 3 data ready for transmission when IN token is received. MOTOROLA MPC823e REFERENCE MANUAL 16-379...
Page 834 16.10.9 Using the USB Controller as a Host This section describes the full implementation of host mode, which is available for Revision B (and later) of the MPC823e silicon. Earlier revisions of the MPC823e only support high-speed (12Mbs) host mode operation.
Page 835 29. Write 0x80 to the USCOM to start filling the TX FIFO with endpoint 0 data ready for transmission when IN token is received. 30. Write 0x81 to the USCOM to start filling the TX FIFO with endpoint 1 data ready for transmission when IN token is received. MOTOROLA MPC823e REFERENCE MANUAL 16-381...
Page 836 (TDM) channels, the internal baud rate generators, or from an external 1 × clock. The Transparent protocol allows the transmitter and receiver to use the external synchronization pin. 16-382 MPC823e REFERENCE MANUAL MOTOROLA...
Page 837 SMCLK originates from an external pin or one of the two internal baud rate generators. Refer to Section 16.7.8 Nonmultiplexed Serial Interface Configuration for more details. MOTOROLA MPC823e REFERENCE MANUAL 16-383...
Page 838 When the serial management controllers are configured to operate in GCI mode, their memory structure is predefined as one half-word long for transmit and one half-word long for receive. For more information on these half-word structures, refer to Section 16.11.8 The SMCx in GCI Mode . 16-384 MPC823e REFERENCE MANUAL MOTOROLA...
Page 839 Once initialized, most parameter RAM values do not need to be accessed in your software since most of the activity is centered around the transmit and receive buffer descriptors and not the parameter RAM. However, if you access the parameter RAM, note the following restrictions. MOTOROLA MPC823e REFERENCE MANUAL 16-385...
Page 840 First Word of Protocol-Specific Area SMCx Base + 36 Last Word of Protocol-Specific Area NOTE: You are only responsible for initializing the items in bold. SMCx Base = (IMMR & 0xFFFF0000) + 0x3E80 (SMC1) and 0x3F80 (SMC2). 16-386 MPC823e REFERENCE MANUAL MOTOROLA...
Page 841 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 842 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 843 MPC823e writes to a receive buffer on a serial management controller before it moves on to the next buffer. The MPC823e can write fewer bytes to the buffer than MRBLR if a condition, such as an error or end-of-frame occurs, but it never writes more bytes than the MRBLR value.
Page 844 RAM values. If you want to disable the SCCs, USB, SMCs, SPI, and I C, use the CPM command register (described in Section 16.2.6.1 CPM Command Register ) to reset the communication processor module with a single command. 16-390 MPC823e REFERENCE MANUAL MOTOROLA...
Page 845 PARAMETERS command in step 2. 4. Set the REN bit in the SMCMR. When the E bit is set in the RX buffer descriptor, reception begins immediately using the RX buffer descriptor indicated by the RBPTR. MOTOROLA MPC823e REFERENCE MANUAL 16-391...
Page 846 • Built-in multidrop modes • Freeze mode for implementing flow control • Isochronous operation (1 × clock ) • Interrupts on special control character reception • Ability to transmit data on demand using the transmit on demand register 16-392 MPC823e REFERENCE MANUAL MOTOROLA...
Page 847 When there is a message to transmit, the SMCx UART controller fetches the data from memory and starts transmitting the message. MOTOROLA MPC823e REFERENCE MANUAL 16-393...
Page 848 Break Count Register (Transmit) SMCx Base +32 R_MASK Half-word Temporary Bit Mask NOTE: You are only responsible for initializing the items in bold. SMCx Base = (IMMR & 0xFFFF0000) + 0x3E80 (SMC1) and 0x3F80 (SMC2). 16-394 MPC823e REFERENCE MANUAL MOTOROLA...
Page 849 The transmitter can generate an idle sequence before starting a new message and the receiver can close a buffer when an idle sequence is found. MOTOROLA MPC823e REFERENCE MANUAL 16-395...
Page 850 BRKCR entry and then reverts to idle or sends data if the RESTART TRANSMIT command was issued before completion. When the break is completed, the transmitter sends at least one idle character before transmitting any data to guarantee recognition of a valid start bit. 16-396 MPC823e REFERENCE MANUAL MOTOROLA...
Page 851 BRKLN counter. If the channel was in the middle of buffer processing when the break was received, the buffer is closed with the BR bit in the receive buffer descriptor set and the receive interrupt is generated if it is enabled. MOTOROLA MPC823e REFERENCE MANUAL 16-397...
Page 852 0-3 to CLEN. SL—Stop Length 0 = One stop bit. 1 = Two stop bits. PEN—Parity Enable 0 = No parity. 1 = Parity is enabled for the transmitter and receiver, depending on the PM bit setting. 16-398 MPC823e REFERENCE MANUAL MOTOROLA...
Page 853 RESERVED RESERVED OFFSET + 0 DATA LENGTH OFFSET + 2 OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. MOTOROLA MPC823e REFERENCE MANUAL 16-399...
Page 854 The communication processor module writes this bit after the received data is in the associated data buffer. 0 = No break sequence is received. 1 = A break sequence is received and the buffer closes. 16-400 MPC823e REFERENCE MANUAL MOTOROLA...
Page 855 This field always points to the first location of the associated data buffer and must be even. The buffer can reside in internal or external memory. The communication processor module writes this bit after the received data is in the associated data buffer. MOTOROLA MPC823e REFERENCE MANUAL 16-401...
Page 856 POINTER 32-BIT BUFFER POINTER (MAX_IDL) WITH THIS BUFFER 10 CHARS 5 CHARS LONG IDLE PERIOD CHARACTERS RECEIVED BY UART PRESENT FOURTH CHARACTER TIME TIME HAS FRAMING ERROR! Figure 16-118. SMCx UART Receive Buffer Descriptor Example 16-402 MPC823e REFERENCE MANUAL MOTOROLA...
Page 857 0 = No interrupt is generated after this buffer is serviced. 1 = The TX bit in the SMCE–UART register is set when this buffer is serviced. Transmission can cause an interrupt if it is enabled. MOTOROLA MPC823e REFERENCE MANUAL 16-403...
Page 858 8 bits, in which this field is even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. The buffer can reside in internal or external memory. 16-404 MPC823e REFERENCE MANUAL MOTOROLA...
Page 859 FIFO. You must wait two character times to be sure that the data is completely sent over the transmit pin. MOTOROLA MPC823e REFERENCE MANUAL 16-405...
Page 860 NOTE: The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when the seventh character was written to the SMC transmit FIFO. Figure 16-119. SMCx UART Interrupt Example 16-406 MPC823e REFERENCE MANUAL MOTOROLA...
Page 861 MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC1 UART parameter RAM for the clarity. 11. Set BRKCR to 0x0001, so that if a STOP TRANSMIT command is issued, one break character is sent. MOTOROLA MPC823e REFERENCE MANUAL 16-407...
Page 862 Extract data from the RX buffer descriptor if the RX bit is set in the SMCE–UART. To transmit another buffer, set the R bit in the TX buffer descriptor. 3. Clear the SMCx bit in the CISR. 4. Execute the rfi instruction. 16-408 MPC823e REFERENCE MANUAL MOTOROLA...
Page 863 (every 4 to 16 serial clocks). When there is a message to transmit, a serial management controller fetches the data from memory and starts transmitting the message after synchronization is achieved. MOTOROLA MPC823e REFERENCE MANUAL 16-409...
Page 864 If the CM bit is set in the receive buffer descriptor, the E bit is not cleared, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this data buffer. 16-410 MPC823e REFERENCE MANUAL MOTOROLA...
Page 865 SMSYNx can cause a serial management controller to behave erratically. The transmitter never loses synchronization again, regardless of the state of SMSYNx, until you clear the TEN bit or issue the ENTER HUNT MODE command. MOTOROLA MPC823e REFERENCE MANUAL 16-411...
Page 866 SMSYNx pin can be used again to resynchronize the transmitter or receiver. Refer to Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely disable and reenable a serial management controller. Simply clearing and setting the TEN bit may not be sufficient. 16-412 MPC823e REFERENCE MANUAL MOTOROLA...
Page 867 BEGINS HERE THE BEGINNING OF EITHER TIME-SLOT TDM RX SYNC TDM RX CLOCK TDM RX SMC1 SMC1 AFTER REN IS SET OR AFTER ENTER HUNT MODE COMMAND, RECEPTION BEGINS HERE Figure 16-121. Time-Slot Assigner Synchronization MOTOROLA MPC823e REFERENCE MANUAL 16-413...
Page 868 Transparent transmitter must be disabled and reenabled. Refer to Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely disable and reenable the SMCx Transparent controller. Simply clearing and setting TEN may not be sufficient. 16-414 MPC823e REFERENCE MANUAL MOTOROLA...
Page 869 RAM to their reset state. It must only be issued when the receiver is disabled. The INIT TX AND RX PARAMS command can also be used to reset the receive and transmit parameters. MOTOROLA MPC823e REFERENCE MANUAL 16-415...
Page 870 SM bits of this register. SMCMR–TRANSPARENT FIELD CLEN REVD RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0xA82 (SMC1), 0xA92 (SMC2) Bits 0, 5, and 8–9—Reserved These bits are reserved and must be set to 0. 16-416 MPC823e REFERENCE MANUAL MOTOROLA...
Page 871 10 = Echo mode. 11 = Reserved. TEN—SMCx Transmit Enable 0 = SMCx transmitter disabled. 1 = SMCx transmitter enabled. Note: Once the TEN bit is cleared, it must not be reenabled for at least three serial clocks. MOTOROLA MPC823e REFERENCE MANUAL 16-417...
Page 872 Once the E bit is set, the core must not write any fields of this RX buffer descriptor. Bits 1, 4–5, 7–13, and 15—Reserved These bits are reserved and must be set to 0. 16-418 MPC823e REFERENCE MANUAL MOTOROLA...
Page 873 This field always points to the first location of the associated data buffer, must be even, and can reside in internal or external memory. The communication processor module writes these bits after the received data is placed into the associated data buffer. MOTOROLA MPC823e REFERENCE MANUAL 16-419...
Page 874 0 = No interrupt is generated after this buffer is serviced. 1 = The TX and TXE bits in the SMCE–Transparent register are set when this buffer is serviced. TX and TXE can cause interrupts if they are enabled. 16-420 MPC823e REFERENCE MANUAL MOTOROLA...
Page 875 8 bits, in which case this field must be even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. The buffer can reside in internal or external memory. MOTOROLA MPC823e REFERENCE MANUAL 16-421...
Page 876 This bit indicates that a data buffer has been received on the SMCx channel and its associated RX buffer descriptor is now closed. This bit is set after the last character is written to the buffer. 16-422 MPC823e REFERENCE MANUAL MOTOROLA...
Page 877 MRBLR = 0x0010. 9. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional), and 0x00001000 to RX_BD_Pointer. MOTOROLA MPC823e REFERENCE MANUAL 16-423...
Page 878 MRBLR = 0x0010. 6. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional), and 0x00001000 to RX_BD_Pointer. 16-424 MPC823e REFERENCE MANUAL MOTOROLA...
Page 879 (IOM-2) in ISDN applications • Two serial management controllers support the two sets of circuit interface and monitor channels in SCIT channels 0 and 1 • Full-duplex operation • Local loopback and echo capability for testing MOTOROLA MPC823e REFERENCE MANUAL 16-425...
Page 880 When the communication processor module stores a received data byte in the SMCx receive (RX) buffer descriptor, a maskable interrupt is generated. You can issue the TRANSMIT ABORT REQUEST command and the MPC823e transmits an abort request on the E bit.
Page 881 The communication processor module clears this bit to indicate that the data byte associated with this buffer descriptor is now available to the core. The core sets this bit to indicate that the data byte associated with this buffer descriptor has been read. MOTOROLA MPC823e REFERENCE MANUAL 16-427...
Page 882 This bit is only valid when a serial management controller implements the monitor channel protocol. When it is set, a serial management controller first transmits the buffer data and then transmits the EOM indication on the E bit. 16-428 MPC823e REFERENCE MANUAL MOTOROLA...
Page 883 For circuit interface channel 0, bits 10-13 contain the 4-bit data field and bits 8 and 9 are always written with zeros. For circuit interface channel 1, bits 8-13 contain the 6-bit data field. MOTOROLA MPC823e REFERENCE MANUAL 16-429...
Page 884 • TIMEOUT—This transmitter command can be issued when the MPC823e implements the monitor channel protocol and it is usually issued because the device is not responding or A bit errors are detected. The MPC823e sends an abort request on the E bit at the time this command is issued.
Page 885 00 = GCI or SCIT mode. Required for SMCx GCI or SCIT operation. 01 = Reserved. 10 = UART mode. 11 = Totally transparent mode. DM—Diagnostic Mode 00 = Normal mode. 01 = Local loopback mode. 10 = Echo mode. 11 = Reserved. MOTOROLA MPC823e REFERENCE MANUAL 16-431...
Page 886 This bit indicates when the circuit interface receive buffer is full. MTXB—Monitor Channel Buffer Transmitted This bit indicates that the monitor transmit buffer is now empty. MRXB—Monitor Channel Buffer Received This bit indicates when the monitor receive buffer is full. 16-432 MPC823e REFERENCE MANUAL MOTOROLA...
Page 887 Because the SPI receiver and transmitter are double-buffered, as illustrated in the block diagram below, the effective FIFO size is 2 characters. You can program the MPC823e serial peripheral interface to shift out the most- or least-significant bit first. When the serial peripheral interface is not enabled in the SPMODE register, it consumes very little power.
Page 888 • Supports Maximum Clock Rates of 6.25MHz in Master Mode and 12.5MHz in Slave Mode, Assuming a 25MHz System Clock is Used • Independent Programmable Baud Rate Generator • Programmable Clock Phase and Polarity • Open-Drain Output Pins Support Multimaster Configuration • Local Loopback Capability for Testing 16-434 MPC823e REFERENCE MANUAL MOTOROLA...
Page 889 SPIMOSI pin and shifts out the transmitted data to the SPIMISO pin. The SPISEL pin provided by the MPC823e is the enable input to the SPI slave. When the serial peripheral interface is operating in a multimaster environment, the SPISEL pin is still an input and is used to detect an error condition when more than one master is operating.
Page 890 When the serial peripheral interface is in master mode, it transmits a message to the peripheral or slave, which sends back an immediate reply. When the MPC823e has more than one slave, it can use the general-purpose parallel I/O pins to selectively enable different slaves.
Page 891 For instance, SYSTEMCLK/4 in master mode and SYSTEMCLK/2 in slave mode. If multiple characters are to be transmitted, you must insert gaps between them so that it will not exceed the maximum sustained data rate. MOTOROLA MPC823e REFERENCE MANUAL 16-437...
Page 892 You must not configure the SPI buffer descriptor tables to overlap with the tables of the USB, SMCx, and SCCx or erratic operation will occur. RBASE and TBASE must contain a value that is divisible by eight. 16-438 MPC823e REFERENCE MANUAL MOTOROLA...
Page 893 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 894 MRBLR value. Buffers you supply for the MPC823e to use must always be at least as long as MRBLR. The transmit buffers for a serial peripheral interface are not affected by the value you program into MRBLR and they can have different lengths, as needed.
Page 895 RAM to their reset state and must only be issued when the receiver is disabled. The INIT TX AND RX PARAMS command can also be used to reset the receive and transmit parameters. MOTOROLA MPC823e REFERENCE MANUAL 16-441...
Page 896 FRAME STATUS DATA LENGTH TX DATA BUFFER DATA POINTER POINTER TO SPI TX RING RX BD RING POINTER TO SPI RX DATA BUFFER FRAME STATUS RX RING DATA LENGTH DATA POINTER Figure 16-123. SPI Memory Format 16-442 MPC823e REFERENCE MANUAL MOTOROLA...
Page 897 In slave mode, the clock source is the SPICLK pin. 0 = Use the BRGCLK as the input to the SPI baud rate generator. 1 = Use the BRGCLK/16 as the input to the SPI baud rate generator. MOTOROLA MPC823e REFERENCE MANUAL 16-443...
Page 898 (16 bits) in memory. 0011 = 4-bit character length. 0100 = 5-bit character length. 0101 = 6-bit character length. 0110 = 7-bit character length. 0111 = 8-bit character length. • • • 1111 = 16-bit character length. 16-444 MPC823e REFERENCE MANUAL MOTOROLA...
Page 899 Data Selected: ghij_klmn_xxxr_stuv Data Transmitted for REV=0: nmlk_jihg__vuts_r Data Transmitted for REV=1: r_stuv__ghij_klmn Example 4 LEN = 0xf (Data Size = 16) Data Selected: ghij_klmn_opqr_stuv Data Transmitted for REV=0: nmlk_jihg__vuts_rqpo Data Transmitted for REV=1: opqr_stuv__ghij_klmn MOTOROLA MPC823e REFERENCE MANUAL 16-445...
Page 900 Figure 16-124. SPI Transfer Format If CP is Set to 0 SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (FROM MASTER) SPIMISO (FROM SLAVE) SPISEL NOTE: Q = Undefined Signal Figure 16-125. SPI Transfer Format If CP is Set to 1 16-446 MPC823e REFERENCE MANUAL MOTOROLA...
Page 901 Once the E bit is set, the core must not write any fields of this RX buffer descriptor. Bit 1, 5, and 7–13—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-447...
Page 902 This indicates a synchronization problem between multiple masters on the SPI bus. The serial peripheral interface writes this bit after the received data is placed into the associated data buffer. 16-448 MPC823e REFERENCE MANUAL MOTOROLA...
Page 903 1 = The data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. You cannot write any fields of this buffer descriptor once this bit is set. Bits 1, 5, and 7–13—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-449...
Page 904 This bit indicates that this buffer is closed because the SPISEL pin was asserted when the serial peripheral interface was in master mode. This indicates a synchronization problem between multiple masters on the SPI bus. The serial peripheral interface writes this bit after it finishes transmitting the associated data buffer. 16-450 MPC823e REFERENCE MANUAL MOTOROLA...
Page 905 SPI input clocks and select signal are received. This bit is automatically cleared after one system clock cycle. Bits 1–7—Reserved. These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-451...
Page 906 RXB—RX Buffer This bit indicates that a buffer has been received. It set after the last character is written to the receive buffer and the RX buffer descriptor is closed. 16-452 MPC823e REFERENCE MANUAL MOTOROLA...
Page 907 16 bytes, so MRBLR = 0x0010. 8. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional), and 0x00001000 to RX_BD_Pointer. MOTOROLA MPC823e REFERENCE MANUAL 16-453...
Page 908 0x00001000 to RX_BD_Pointer. 8. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xB800 to TX_BD_Status, 0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer. 16-454 MPC823e REFERENCE MANUAL MOTOROLA...
Page 909: Handling Interrupts In The Spi
To transmit another buffer, simply set the R bit of the TX buffer descriptor, the E bit of the RX buffer descriptor, and the STR bit of the SPCOM register. 3. Clear the SPI bit in the CISR. 4. Execute the rfi instruction. MOTOROLA MPC823e REFERENCE MANUAL 16-455...
Page 910 16.13 THE I C CONTROLLER ® The inter-integrated circuits (I ) controller enables the MPC823e to exchange data with a number of other I C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I C controller is a synchronous, multimaster bus that is used to connect several integrated circuits on a board.
Page 911 ACK after a data byte is transmitted, the I C master generates a stop condition and transmission stops. A stop condition is when the SDA signal makes a low to high transition while the SCL signal remains high, as illustrated in Figure 16-127. MOTOROLA MPC823e REFERENCE MANUAL 16-457...
Page 912 I2MOD and I2BRG registers. The I2ADD register does not need to be programmed when you are operating the I C controller in single-master mode. Enable the C controller by setting the EN bit in the I2MOD register. 16-458 MPC823e REFERENCE MANUAL MOTOROLA...
Page 913 Note: Some slave devices, such as serial E2PROMs, may have a minimum write cycle time. For these devices, the I C controller must wait a minimum amount of time after a write before initiating the next read or write. The required delay must be implemented in software. MOTOROLA MPC823e REFERENCE MANUAL 16-459...
Page 914 N bytes of data to receive from the slave device. DEVICE ADDR DATA BYTE NOTE: DATA AND ACK ARE REPEATED N TIMES. Figure 16-131. Byte Read from Device without Internal Addresses 16-460 MPC823e REFERENCE MANUAL MOTOROLA...
Page 915 N bytes of data. The first byte of the TX buffer descriptor must contain the address of the MPC823e I device’s own address, which is in the I2CADD register, followed by the write bit asserted (R/ W = 0).
Page 916 Other TX buffer descriptor control bits, such as W, I, and L, may also be set. You must then set the STR bit in the I2COM register to prepare the slave to respond to the master. 16-462 MPC823e REFERENCE MANUAL MOTOROLA...
Page 917 Furthermore, you must not configure the buffer descriptor tables of the I C controller to overlap because erratic operation will occur. RBASE and TBASE must contain a value that is divisible by eight. MOTOROLA MPC823e REFERENCE MANUAL 16-463...
Page 918 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed in comparison to the Motorola mode. This mode is supported only for 32-bit port size memory.
Page 919 MRBLR value. Buffers you supply for the MPC823e to use must always be at least as long as MRBLR. The I transmit buffers are not affected by the value you program into MRBLR and they can be different lengths.
Page 920 RAM to their reset state and must only be issued when the receiver is disabled. The INIT TX AND RX PARAMS command can also be used to reset the receive and transmit parameters. 16-466 MPC823e REFERENCE MANUAL MOTOROLA...
Page 921 DATA LENGTH TX DATA BUFFER DATA POINTER POINTER TO I2C TX RING RX BUFFER DESCRIPTOR RING POINTER TO I2C RX DATA BUFFER RX RING FRAME STATUS DATA LENGTH DATA POINTER Figure 16-132. I C Memory Format MOTOROLA MPC823e REFERENCE MANUAL 16-467...
Page 922 01 = Use the BRGCLK/16 as the input to the I C baud rate generator. 10 = Use the BRGCLK/8 as the input to the I C baud rate generator. 11 = Use the BRGCLK/4 as the input to the I C baud rate generator. 16-468 MPC823e REFERENCE MANUAL MOTOROLA...
Page 923 RESERVED OFFSET + 0 DATA LENGTH OFFSET + 2 OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. MOTOROLA MPC823e REFERENCE MANUAL 16-469...
Page 924 1 = This buffer contains the last character of the message. OV—Overrun This bit indicates that a receiver overrun has occurred during reception. The I C controller writes this bit after the received data is placed into the associated data buffer. 16-470 MPC823e REFERENCE MANUAL MOTOROLA...
Page 925 1 = The data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. You cannot write any fields of this buffer descriptor once this bit is set. Bits 1 and 6–12—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-471...
Page 926 CL—Collision This bit indicates that transmission has been aborted because the transmitter was lost while arbitrating for the bus. The I C controller writes this bit after it finishes transmitting the associated data buffer. 16-472 MPC823e REFERENCE MANUAL MOTOROLA...
Page 927 (IMMR & 0xFFFF0000) + 0x864 NOTE: = Undefined. — SAD— Slave Address 0–6 This field holds the slave address for the I C port. Bit 7—Reserved This bit is reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 16-473...
Page 928 I C transmit buffer and start transmitting when it receives an address byte that matches the slave address with the R/W bit set to 1. The STR bit is always read as a zero. 16-474 MPC823e REFERENCE MANUAL MOTOROLA...
Page 929 RXB—RX Buffer This bit indicates that a buffer has been received. This bit is set after the last character is written to the receive buffer and the RX buffer descriptor is closed. MOTOROLA MPC823e REFERENCE MANUAL 16-475...
Page 930 C controller operates the SCL at 391kHz. A system frequency of 50MHz is assumed. The SDA and SCL pins of the MPC823e are connected to an external 5V power supply with 6.8K Ohm to 10K Ohm resistors. 1. Configure the port B pins to enable the SDA and SCL pins. Write PBPAR, PBDIR, and PBODR bits 26 and 27 with ones.
Page 931 A, B, and C. The functions are grouped in such a way as to maximize the usefulness of the pins in the greatest number of MPC823e applications. It may be difficult to fully understand the pin assignment capability described in this section until you better understand the CPM peripherals themselves.
Page 932 PADIR bit is cleared and configured as an output if the corresponding bit is set. All PAPAR and PADIR bits are cleared at system reset, which configures all port A pins as general-purpose input pins. 16-478 MPC823e REFERENCE MANUAL MOTOROLA...
Page 933 PADAT is read, the state of the port pin is read. If an input to a peripheral is not supplied from a pin, then a default value is supplied to the on-chip peripheral as listed in Table 16-41. MOTOROLA MPC823e REFERENCE MANUAL 16-479...
Page 934 ADDR (IMMR & 0xFFFF0000) + 0x956 Bits 0–3—Reserved These bits are reserved and must be set to 0. D4–D15—Data Pins 4-15 The value written into these bits may be read on the Port A pins. 16-480 MPC823e REFERENCE MANUAL MOTOROLA...
Page 935 0 = General-purpose I/O. The peripheral functions of the pin are not used. 1 = Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits. MOTOROLA MPC823e REFERENCE MANUAL 16-481...
Page 936 PA14 is configured as a general-purpose I/O pin, then the USBOE output is not externally connected. PADAT BIT 15 USBRXD/PA15 OUTPUT LATCH 16 BITS PADIR USBRXD 16 BITS PAPAR Figure 16-133. Parallel Block Diagram For PA15 16-482 MPC823e REFERENCE MANUAL MOTOROLA...
Page 937 PADIR bit is a 1, PA4 can be the TOUT2 pin. If the PA4 pin is a general-purpose I/O pin, then the input to the on-chip CLK4 function is grounded. Refer to Section 16.7 The Serial Interface with Time-Slot Assigner for more details. MOTOROLA MPC823e REFERENCE MANUAL 16-483...
Page 938 SMRXD1/L1RXDB RXD3 SMRXD1 = VCC;RXD3 = GND PB23 PORT B23 SMSYN1/L1TSYNCB SDACK1 SMSYN1 = GND PB22 PORT B22 SMSYN2/L1RSYNCB SDACK2 SMSYN2 = GND PB19 PORT B19 L1ST1 LCD_B — PB18 PORT B18 L1ST2 RTS2 — 16-484 MPC823e REFERENCE MANUAL MOTOROLA...
Page 939: The Port B Registers
1 = The I/O pin is an open-drain driver. As an output, the pin is actively driven low. Otherwise, it is three-stated. Note: SMTXD1 cannot be set as an open-drain driver, regardless of how this register is set. MOTOROLA MPC823e REFERENCE MANUAL 16-485...
Page 940 ADDR (IMMR & 0xFFFF0000) + 0xAC6 Bits 0–15—Reserved These bits are reserved and must be set to 0. D16–31—Data Pins 16–31 These bits contain data can be read or written from the port B pins. 16-486 MPC823e REFERENCE MANUAL MOTOROLA...
Page 941 (IMMR & 0xFFFF0000) + 0xABA Bits 0–15—Reserved These bits are reserved and must be set to 0. DR16–DR31—Data Direction Pins 16-31 0 = The corresponding pin is an input. 1 = The corresponding pin is an output. MOTOROLA MPC823e REFERENCE MANUAL 16-487...
Page 942 0 = General-purpose I/O. The peripheral functions of the pin are not used. 1 = Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits, such as those in the PBDIR. 16-488 MPC823e REFERENCE MANUAL MOTOROLA...
Page 943 If a port C pin is configured as an input, data written to PCDAT register is still stored in the output latch, but is prevented from reaching the port pin. In this case, when PCDAT register is read, the state of the port pin is read. MOTOROLA MPC823e REFERENCE MANUAL 16-489...
Page 944 4. Set the PCINT bit to discover the edges that cause the interrupts. 5. Write the corresponding CIMR bit with a 1 so that interrupts can be sent to the core. 6. Read the pin value using the PCDAT register. 16-490 MPC823e REFERENCE MANUAL MOTOROLA...
Page 945 PCINT. Note: Do not program the DREQ1 and DREQ2 pins to assert external requests to the RISC microcontroller, unless instructed to do so by Motorola as part of a RAM microcode package. Otherwise, erratic behavior will occur. 16.14.9 Port C Registers You can communicate with port C using five registers.
Page 946 (IMMR & 0xFFFF0000) + 0x960 Bits 0–3—Reserved These bits are reserved and must be set to 0. DR4–DR15—Data Direction Pins 4–15 0 = The corresponding pin is an input. 1 = The corresponding pin is an output. 16-492 MPC823e REFERENCE MANUAL MOTOROLA...
Page 947 If PCDIR configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the PCINT bits. 1 = PCx is connected to the corresponding SCCx signal input in addition to being a general-purpose interrupt pin. MOTOROLA MPC823e REFERENCE MANUAL 16-493...
Page 948 1 = PCx becomes an external request to the RISC microcontroller instead of being a general-purpose interrupt pin. The corresponding PCINT bits control when a request is generated. Note: DREQx must only be set if you are using IDMA. 16-494 MPC823e REFERENCE MANUAL MOTOROLA...
Page 949 EDM4–EDM15—Edge Detect Mode for Lines 4–15 The corresponding port C line asserts an interrupt request. 0 = Any change on PCx generates an interrupt request. 1 = High-to low change on PCx generates an interrupt request. MOTOROLA MPC823e REFERENCE MANUAL 16-495...
Page 950 PORT D14 PD13 PORT D13 PD12 PORT D12 PD11 PORT D11 PD10 PORT D10 PORT D9 PORT D8 PORT D7 FIELD PORT D6 LCD_AC/OE BLANK PORT D5 FRAME/VSYNC PORT D4 LOAD/HSYNC PORT D3 SHIFT/CLK VCLK 16-496 MPC823e REFERENCE MANUAL MOTOROLA...
Page 951: Port D Registers
(IMMR & 0xFFFF0000) + 0x970 Bits 0–2—Reserved These bits are reserved and must be set to 0. DR3–DR15—Data Direction Pins 3–15 0 = The corresponding pin is an input. 1 = The corresponding pin is an output. MOTOROLA MPC823e REFERENCE MANUAL 16-497...
Page 952 (CIPR) where all interrupt sources are assigned one programmable priority level (0–7) before the request for an interrupt is sent to the U-Bus. An overview of the MPC823e interrupt structure is illustrated in Figure 16-135. The lower half of the figure illustrates the CPM interrupt controller.
Page 953 IREQ LEVEL 3 PCMCIA LEVEL 2 LEVEL 1 LEVEL 0 DEBUG DEBUG SYSTEM INTERFACE UNIT PORT C[4:15] TIMER1 TIMER2 TIMER3 TIMER4 SCC2 SCC3 SMC1 SMC2 IDMA1 IDMA2 SDMA RISC TIMERS Figure 16-135. MPC823e Interrupt Structure 16-499 MPC823e REFERENCE MANUAL MOTOROLA...
Page 954 Within the CPM interrupt level, the sources are assigned a priority structure. On the MPC823e, you have some flexibility with the relative priority of the interrupt sources. Once an unmasked interrupt source is pending in the CIPR, the CPM interrupt controller sends an interrupt request to the U-Bus at level 0, 1, 2, 3, 4, 5, 6, or 7.
Page 955 This highest priority source is dynamically programmable in the CICR and it allows you to change a normally low priority source into a high priority source for a certain period of time. 16-501 MPC823e REFERENCE MANUAL MOTOROLA...
Page 956 SCCb (Spread) Timer 2 RISC Timer Table Parallel I/O–PC11 Parallel I/O–PC10 SCCc (Spread) Timer 3 Parallel I/O–PC9 Parallel I/O–PC8 Parallel I/O–PC7 SCCd (Spread) Timer 4 Parallel I/O–PC6 SMC1 SMC2 Parallel I/O–PC5 Parallel I/O–PC4 Lowest Reserved — MOTOROLA MPC823e REFERENCE MANUAL 16-502...
Page 957 Table 16-46 shows the interrupt sources that have multiple interrupting events and Figure 16-136 illustrates an example of how the masking occurs using SCC2 as an example. 16-503 MPC823e REFERENCE MANUAL MOTOROLA...
Page 958 CIVR. For CPM interrupts, the CPM interrupt controller passes an interrupt vector corresponding to the unmasked pending interrupt of the highest priority. The CPM interrupt controller encoding of the five low-order bits of the interrupt vector is shown in Table 16-46. MOTOROLA MPC823e REFERENCE MANUAL 16-504...
Page 959 Reserved 01101 Timer 3 01100 Parallel I/O—PC9 01011 Parallel I/O—PC8 01010 Parallel I/O—PC7 01001 Reserved 01000 Timer 4 00111 Parallel I/O—PC6 00110 00101 SMC1 00100 SMC2 00011 Parallel I/O—PC5 00010 Parallel I/O—PC4 00001 Error 00000 16-505 MPC823e REFERENCE MANUAL MOTOROLA...
Page 960 01 = SCC2 will assert its request in the SCCd position. 10 = SCC3 will assert its request in the SCCd position. 11 = Neither the USB or SCCx will assert its request in the SCCd position. MOTOROLA MPC823e REFERENCE MANUAL 16-506...
Page 961 This field specifies the 5-bit interrupt number of the single CPM interrupt controller’s interrupt source that is advanced to the highest priority in the table. These bits can be dynamically modified. To keep the original priority order intact, simply program these bits to 11111. 16-507 MPC823e REFERENCE MANUAL MOTOROLA...
Page 962 CIPR bit is not cleared if an event register exists for that interrupt source. Event registers only exist for interrupt sources that have multiple source events. For example, the serial communication controllers have multiple events that cause SCCx interrupts. MOTOROLA MPC823e REFERENCE MANUAL 16-508...
Page 963 CIMR TIMER TIMER FIELD PC15 SCC2 SCC3 PC14 PC13 PC12 SDMA IDMA1 IDMA2 R–TT RESET ADDR (IMMR & 0xFFFF0000) + 0x948 TIMER TIMER FIELD PC11 PC10 SMC1 SMC2 RESET ADDR (IMMR & 0xFFFF0000) + 0x94A 16-509 MPC823e REFERENCE MANUAL MOTOROLA...
Page 964 For example, the TIMER1 interrupt routine could interrupt the handling of the TIMER2 routine using a special nesting technique described earlier. During this time, you can see both the TIMER2 and the TIMER1 bits simultaneously set in the CISR. MOTOROLA MPC823e REFERENCE MANUAL 16-510...
Page 965 2. Read the vector to access the interrupt handler. 3. Handle the event associated with a change in the state of the PC6 pin. 4. Clear the PC6 bit in the CISR. 5. Execute the rfi instruction. 16-511 MPC823e REFERENCE MANUAL MOTOROLA...
Page 966 7. Execute the rfi instruction. If any unmasked bits (those not cleared by the software or set by the MPC823e during the execution of this handler) in the USBE remain at this time, this interrupt source is pending again after the rfi instruction.
Page 967 Figure 17-1. In this system configuration, you must accomplish electrical isolation between the sockets and system bus using external buffers and bus transceivers. These buffers also provide the voltage conversion needed from the MPC823e’s 3.3V to 5V cards. They must be powered by the card V .
Page 968 OE_B (IORD),(IOWR) (IORD_B),(IOWR_B) RESET_B BUFFER WITH OE POE_B TRANSPARENT LATCH WITH OE A[6:31] ADDRESS_B[25:0] REG_B ALE_B VCC_B WAIT_B, IOIS16_B RDY/BSY_B, BVD1_B,BVD2_B CHIP VDD CD1_B, CD2_B, VS1_B, VS2_B SPKROUT Figure 17-1. System with One PCMCIA Socket 17-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 969 The CEx signals can be configured to duplicate the values of the A[22:23] signals. At the end of the PCMCIA access, these lines will be always negated. See Table 17-1 for details. This feature can be used to access devices supporting IDE/ATA protocols. Table 17-1. Card Enable as Driven by the MPC823e PORT ACCESS...
Page 970 • External Transceiver Direction (R/W)—Output. This signal is part of the MPC823e bus. It is asserted or driven high during any read cycles of the MPC823e and negated or driven low during write cycles. It is used in the PCMCIA interface to control the direction of the data bus transceivers.
Page 971 PCMCIA Interface 17.3.2 The PCMCIA Input Port Signals The MPC823e provides synchronization, transition detection, optional interrupt generation and a means for the software to read the signal state. This function is not necessarily specific to PCMCIA and the signals can be used as a general-purpose input port with edge detection and interrupt capability.
Page 972 The following signals are used by a PCMCIA slot to control the RESET signal to the card and the output enable of the buffers to the card. The MPC823e allows software to control the output signal state. This function is not necessarily specific to the PCMCIA interface and these signals, which appear on the OP[2:3] pins, may be used by a system as a general- purpose output port.
Page 973 Table 17-3 shows a worst case example of programming PCMCIA host for I/O cycle. Table 17-3. Host Programming For I/O Cards STP(1) 20ns 30ns 40ns 62ns 83ns Setup time worst case is for write, so setup = data_setup_before_IORD +1 system clock. MOTOROLA MPC823e REFERENCE MANUAL 17-7...
Page 974 PCMCIA card to be reset or to disable the output drive of the external latches. 17.4.6 DMA The MPC823e’s DMA module with the CPM microcode provides two independent DMA channels. The PCMCIA module can be programmed to generate control for an I/O device implemented as a PCMCIA card to act on a DMA transfer.
Page 975 CBCD1 CBRDY RESERVED RESET — — — — — — — — — ADDR (IMMR & 0xFFFF0000) + 0xF0 NOTE: — = Undefined. Bits 0–15—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 17-9...
Page 976 CBRDY—Card B RDY/BSY_B/IREQ_B/IRQ If Card B and its socket are configured for memory interface operation, CBRDY is: 0 = Card B is busy. 1 = Card B is ready to accept a new data transfer operation. 17-10 MPC823e REFERENCE MANUAL MOTOROLA...
Page 977 These bits are reserved and must be set to 0 CBVS1_C—Card B Voltage Sense 1 Change 0 = Signal is changed. 1 = Signal is unchanged. CBVS2_C—Card B Voltage Sense 2 Change 0 = Signal is changed. 1 = Signal is unchanged. MOTOROLA MPC823e REFERENCE MANUAL 17-11...
Page 978 Note: Writing logic one to each bit reset its value (zero), except for bit 9, which is always set to one. To reset the value of bits 24 and 25, you must remove the external source of the interrupt. 17-12 MPC823e REFERENCE MANUAL MOTOROLA...
Page 979 1 = Enable interrupt on changes in the relevant pin. CB_ECD1—Card B Enable for Card Detect 1 0 = Disable interrupt on any change in the relevant pin. 1 = Enable interrupt on changes in the relevant pin. MOTOROLA MPC823e REFERENCE MANUAL 17-13...
Page 980 CB_ERDY_F—Card B Enable for RDY/IRQ Falling Edge 0 = Disable interrupt on any change in the relevant pin. 1 = Enable interrupt on changes in the relevant pin. Bits 28–31—Reserved These bits are reserved and must be set to 0. 17-14 MPC823e REFERENCE MANUAL MOTOROLA...
Page 981 Note: If the PCMCIA controller is programmed to enable internal DMA, then the port C registers must not be configured to select DREQ2. Bits 18–23—Reserved These bits are reserved and must be set to 0. MOTOROLA MPC823e REFERENCE MANUAL 17-15...
Page 982 0xA0 (PBR4), 0xA8 (PBR5), 0xB0 (PBR6), 0xB8 (PBR7) FIELD RESET — (IMMR & 0xFFFF0000) + 0x80 (PBR0), 0x88 (PBR1), 0x90 (PBR2), 0x98 (PBR3), ADDR 0xA0 (PBR4), 0xA8 (PBR5), 0xB0 (PBR6), 0xB8 (PBR7) NOTE: — = Undefined. PBA—PCMCIA Base Address 17-16 MPC823e REFERENCE MANUAL MOTOROLA...
Page 983 The bank size is calculated from BSIZE as: GRAYCODE BSIZE BankSize 00000 = 1 bytes. 00001 = 2 bytes. 00011 = 4 bytes. 00010 = 8 bytes. 00110 = 16 bytes. 00111 = 32 bytes. MOTOROLA MPC823e REFERENCE MANUAL 17-17...
Page 984 10111 = 64M. The calculated bank size is used as a mask (MASK) to determine a valid PCMCIA address as follows: If ((Address & MASK) == (PBA & MASK)) Valid PCMCIA access else invalid PCMCIA access 17-18 MPC823e REFERENCE MANUAL MOTOROLA...
Page 985 1011= Address to Strobe assertion 11 clock cycles. 1100= Address to Strobe assertion 12 clock cycles. 1101= Address to Strobe assertion 13 clock cycles. 1110= Address to Strobe assertion 14 clock cycles. 1111= Address to Strobe assertion 15 clock cycles. MOTOROLA MPC823e REFERENCE MANUAL 17-19...
Page 986 11111= Strobe asserted 31 clock cycles. 00000= Strobe asserted 32 clock cycles. PPS—PCMCIA Port Size This field specifies the port size of this PCMCIA window. 0 = 8-bit port size. 1 = 16-bit port size. 17-20 MPC823e REFERENCE MANUAL MOTOROLA...
Page 987 (machine check interrupt) will occur. PV—PCMCIA Valid This bit indicates that the contents of the PCMCIA base register and option register pair are valid. 0 = This bank is invalid. 1 = This bank is valid MOTOROLA MPC823e REFERENCE MANUAL 17-21...
Page 988: Pcmcia Controller Timing Examples
17.6 PCMCIA CONTROLLER TIMING EXAMPLES CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-3. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3, PSHT = 1) 17-22 MPC823e REFERENCE MANUAL MOTOROLA...
Page 989 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-4. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 2, PSL = 4, PSHT = 1) MOTOROLA MPC823e REFERENCE MANUAL 17-23...
Page 990 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-5. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3, PSHT = 0) 17-24 MPC823e REFERENCE MANUAL MOTOROLA...
Page 991 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCWE WAIT_B DATA PSST PSHT Figure 17-6. PCMCIA Single Beat Write Cycle (PRS = 2, PSST = 1, PSL = 3, PSHT = 1) MOTOROLA MPC823e REFERENCE MANUAL 17-25...
Page 992 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IOWR_B WAIT_B DATA IOIS16_B PSST PSHT Figure 17-7. PCMCIA Single Beat Write Cycle (PRS = 3, PSST = 1, PSL = 4, PSHT = 3) 17-26 MPC823e REFERENCE MANUAL MOTOROLA...
Page 993 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IOWR_B WAIT_B DATA PSST WAIT DELAY PSHT Figure 17-8. PCMCIA Single Beat Write with Wait (PRS = 3, PSST = 1, PSL = 3, PSHT = 0) MOTOROLA MPC823e REFERENCE MANUAL 17-27...
Page 994 PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IORD_B WAIT_B DATA PSST WAIT DELAY PSHT Figure 17-9. PCMCIA Single Beat Read with Wait (PRS = 3, PSST = 1, PSL = 3, PSHT = 1) 17-28 MPC823e REFERENCE MANUAL MOTOROLA...
Page 995 CLKOUT A[0:31] RD/WR BURST ALE_B IOWR DATA IOIS16_B PSHT PSST Figure 17-10. PCMCIA I/O Read of a 16-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0) MOTOROLA MPC823e REFERENCE MANUAL 17-29...
Page 996 RD/WR BURST ALE_B IOWR DATA IOSI16_B PSST PSHT PSST PSHT Figure 17-11. PCMCIA I/O Read of an 8-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0 17-30 MPC823e REFERENCE MANUAL MOTOROLA...
Page 997 A[0:31] AT=0XF AT=0XF RD/WR BURST CE[1:2] ALE_B IORD PCOE SIZE SIZE=WORD SIZE=HALF DATA PSST PSHT PSST PSHT Figure 17-12. PCMCIA DMA Read Cycle (PRS = 4, PSST = 1, PSL = 3, PSHT = 0) MOTOROLA MPC823e REFERENCE MANUAL 17-31...
Page 998 SECTION 18 LCD CONTROLLER The MPC823e contains an on-chip LCD controller that can be used to drive an LCD panel display. The integrated LCD controller shortens access time, reduces power consumption, and saves system board space by not using external glue logic. The LCD controller can interface with a variety of passive, active, dual-scan, single-scan, and smart LCD panels.
Page 999 (one column in the upper section and one in the lower section). The X shift register can be loaded 1, 2, 4, or 8 bits per shift. 18-2 MPC823e REFERENCE MANUAL MOTOROLA...
Page 1000 These signals are usually provided by an LCD controller that includes a frame buffer RAM for display memory. An example of a complete LCD subsystem is illustrated in Figure 18-2. LCD PANEL X-DRIVERS CONTROLLER LCD ARRAY FRAME BUFFER DC-DC CONVERTER Figure 18-2. LCD Subsystem MOTOROLA MPC823e REFERENCE MANUAL 18-3...

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