Motorola PowerQUICC II MPC8280 Series Reference Manual page 1088

ATM Memory Structure
Table 31-33. Free Buffer Pool Parameter Table (continued)
1
Offset Bits Name
0x0A 0 BUSY
1 RLI
2–7 —
8 EPD
9–15 —
0x0C — FBP_ENTRY
1 Offset from FBT_BASE+RCT[BPOOL] × 16
31.10.5.3 ATM Controller Buffers
Table 31-34 describes properties of the ATM receive and transmit buffers.
AAL
AAL5 Multiple of 48 octets (except last buffer in frame) Burst-aligned (recommended) Any
AAL1 At least 47 octets
AAL0 52-64 octets.
31.10.5.4 AAL5 RxBD
Figure 31-46 shows the AAL5 RxBD.
0 1
Offset + 0x00 E —
Offset + 0x02
Offset + 0x04
Offset + 0x06
31-74
Freescale Semiconductor, Inc.
The CP sets this bit when it tries to fetch buffer pointer with V bit clear.
FCCE[GBPB] is also set. Initialize to zero.
Red-line interrupt. Set by the CP when it fetches a buffer pointer with I = 1.
FCCE[GRLI] is also set. Initialize to zero.
Reserved, should be cleared.
Early packet discard.
0 Normal operation.
1 AAL5 frames in progress are received, but new AAL5 frames associated with
this pool are discarded. Can be used to implement EPD under core control.
Reserved, should be cleared.
Free buffer pool entry. Initialize with the first entry of the free buffer pool. Note that
FBP_ENTRY must be reinitialized with the entry pointed to by FBP_PTR when a
busy state occurs to reenable free buffer pool processing.
Table 31-34. Receive and Transmit Buffers
Receive
Size
2 3 4 5 6
W I L F CM
Rx Data Buffer Pointer (RXDBPTR)
Figure 31-46. AAL5 RxBD
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
Alignment
Burst-aligned (recommended) ≥ 47 octets
Burst-aligned
7 8 9 10 11
— CLP CNG ABRT CPUU LNE CRE
Data Length (DL)
Transmit
Size Alignment
No requirement
No requirement
52–64 octets No requirement
12 13 14 15
MOTOROLA